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发表于 2014-8-17 14:53:06
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本帖最后由 tiancai_ 于 2014-8-17 15:15 编辑
再比如D:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\fifo_generator_v9_3\fifo_generator_top.vhd
-------------------------------------------------------------------------------
-- $Id: fifo_generator_top.vhd,v 1.1 2011/06/02 09:43:54 robertb Exp $
-- Title : Top-level synthesizable file for the FIFO Generator
-- Project : FIFO Generator
-------------------------------------------------------------------------------
-- (c) Copyright 2006 - 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- File : fifo_generator_top.vhd
-- Author : Xilinx
-------------------------------------------------------------------------------
-- Structure:
-- fifo_generator_top
-- |
-- +-- fifo_generator_ramfifo
-- |
-- +-- fifo_generator_v9_3_builtin
-- |
-- +-- fifo_generator_fifo16_patch
-- |
-- +-- fifo_generator_shiftram
-- --
--
-------------------------------------------------------------------------------
-- Description: This is the top-level synthesizable file for the FIFO Generator
-- core. It instantiates one of the various core implementations:
-- builtin, v4 patch, shiftram and ram based FIFOs
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY fifo_generator_v9_3;
USE fifo_generator_v9_3.fifo_generator_v9_3_pkg.ALL; -- for equalIgnoreCase fn
ENTITY fifo_generator_top IS
GENERIC (
---------------------------------------------------------------------------
-- Generic Declarations
---------------------------------------------------------------------------
C_FAMILY : string := "";
C_COMMON_CLOCK : integer := 0;
C_MEMORY_TYPE : integer := 1;
C_IMPLEMENTATION_TYPE : integer := 0;
C_PRELOAD_REGS : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_DIN_WIDTH : integer := 8;
C_WR_DEPTH : integer := 256;
C_WR_PNTR_WIDTH : integer := 8;
C_DOUT_WIDTH : integer := 8;
C_RD_DEPTH : integer := 256;
C_RD_PNTR_WIDTH : integer := 8;
C_PROG_FULL_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL : integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL : integer := 0;
C_USE_ECC : integer := 0;
C_ERROR_INJECTION_TYPE : integer := 0;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_PRIM_FIFO_TYPE : string := "4kx4";
C_FIFO_TYPE : integer := 0; -- 0 = Data FIFO, 1 = Packet FIFO, 2 = Low Latency Sync FIFO 3 = Low Latency Async FIFO
-- 3 = Low Latency Async FIFO, 4 = Low Latency Built-in FIFO
C_USE_SYNC_CLK : integer := 0;
C_BYTE_STRB_WIDTH : integer := 8;
C_USE_INPUT_CE : integer := 0;
C_USE_OUTPUT_CE : integer := 0;
C_AXI_TYPE : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_WR_RST : integer := 0;
C_HAS_RD_RST : integer := 0;
C_HAS_RST : integer := 1;
C_HAS_SRST : integer := 0;
C_DOUT_RST_VAL : string := "";
C_HAS_VALID : integer := 0;
C_VALID_LOW : integer := 0;
C_HAS_UNDERFLOW : integer := 0;
C_UNDERFLOW_LOW : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_HAS_OVERFLOW : integer := 0;
C_OVERFLOW_LOW : integer := 0;
C_HAS_DATA_COUNT : integer := 0;
C_DATA_COUNT_WIDTH : integer := 2;
C_HAS_RD_DATA_COUNT : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 2;
C_USE_FWFT_DATA_COUNT : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 2;
C_FULL_FLAGS_RST_VAL : integer := 1;
C_USE_EMBEDDED_REG : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_MSGON_VAL : integer := 1;
C_ENABLE_RST_SYNC : integer := 1;
C_SYNCHRONIZER_STAGE : integer := 2;
C_COUNT_TYPE : integer := 0;
C_DEFAULT_VALUE : string := "";
C_ENABLE_RLOCS : integer := 0;
C_HAS_BACKUP : integer := 0;
C_HAS_INT_CLK : integer := 0;
C_HAS_MEMINIT_FILE : integer := 0;
C_INIT_WR_PNTR_VAL : integer := 0;
C_MIF_FILE_NAME : string := "";
C_OPTIMIZATION_MODE : integer := 0;
C_RD_FREQ : integer := 1;
C_USE_FIFO16_FLAGS : integer := 0;
C_WR_FREQ : integer := 1;
C_WR_RESPONSE_LATENCY : integer := 1
);
PORT(
--------------------------------------------------------------------------------
-- Input and Output Declarations
--------------------------------------------------------------------------------
BACKUP : IN std_logic := '0';
BACKUP_MARKER : IN std_logic := '0';
INT_CLK : IN std_logic := '0';
CLK : IN std_logic := '0';
WR_CLK : IN std_logic := '0';
RD_CLK : IN std_logic := '0';
RST : IN std_logic := '0';
SRST : IN std_logic := '0';
WR_RST : IN std_logic := '0';
RD_RST : IN std_logic := '0';
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
WR_EN : IN std_logic := '0';
RD_EN : IN std_logic := '0';
-- Optional inputs
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
INJECTDBITERR : IN std_logic := '0';
INJECTSBITERR : IN std_logic := '0';
INPUT_CE : IN std_logic := '0';
OUTPUT_CE : IN std_logic := '0';
END_OF_PACKET : IN std_logic := '0';
BYTE_STROBE : IN std_logic_vector(C_BYTE_STRB_WIDTH-1 DOWNTO 0);
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
FULL : OUT std_logic;
ALMOST_FULL : OUT std_logic;
WR_ACK : OUT std_logic;
OVERFLOW : OUT std_logic;
EMPTY : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
VALID : OUT std_logic;
UNDERFLOW : OUT std_logic;
DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
PROG_FULL : OUT std_logic;
PROG_EMPTY : OUT std_logic;
SBITERR : OUT std_logic;
DBITERR : OUT std_logic
);
END fifo_generator_top;
architecture xilinx of fifo_generator_top is
---------------------------------------------------------------------------
--DEBUG outputs
-- These internal signals are used in place of the output pins of this
-- module. These internal signals are used to tie-off the DEBUG outputs
-- of the XST module when not being used by the core.
---------------------------------------------------------------------------
SIGNAL DEBUG_WR_PNTR : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
SIGNAL DEBUG_RD_PNTR : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0);
SIGNAL DEBUG_RAM_WR_EN : std_logic;
SIGNAL DEBUG_RAM_RD_EN : std_logic;
SIGNAL debug_wr_pntr_w : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
SIGNAL debug_wr_pntr_plus1_w : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
SIGNAL debug_wr_pntr_plus2_w : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
SIGNAL debug_wr_pntr_r : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
SIGNAL debug_rd_pntr_r : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0);
SIGNAL debug_rd_pntr_plus1_r : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0);
SIGNAL debug_rd_pntr_w : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0);
SIGNAL DEBUG_RAM_EMPTY : std_logic;
SIGNAL DEBUG_RAM_FULL : std_logic;
SIGNAL wr_en_ce : std_logic := '0';
SIGNAL rd_en_ce : std_logic := '0';
---------------------------------------------------------------------------
-- Constant definition
---------------------------------------------------------------------------
-- CONSTANT C_RD_EN_MAXFAN : integer := if_then_else((equalIgnoreCase(C_FAMILY,"virtex5")),DEFAULT_RD_EN_MAXFAN_V5, DEFAULT_RD_EN_MAXFAN);
-- CONSTANT C_WR_EN_MAXFAN : integer := if_then_else((equalIgnoreCase(C_FAMILY,"virtex5")),DEFAULT_WR_EN_MAXFAN_V5, DEFAULT_WR_EN_MAXFAN);
CONSTANT C_DEPTH_RATIO_WR : integer
:= if_then_else( (C_WR_DEPTH>C_RD_DEPTH), (C_WR_DEPTH/C_RD_DEPTH), 1);
CONSTANT C_DEPTH_RATIO_RD : integer
:= if_then_else( (C_RD_DEPTH>C_WR_DEPTH), (C_RD_DEPTH/C_WR_DEPTH), 1);
BEGIN
gice: IF (C_USE_INPUT_CE = 1) GENERATE
wr_en_ce <= WR_EN AND INPUT_CE;
END GENERATE gice;
中间略去500字……
END GENERATE gbiv5;
END xilinx;
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发表于 2014-8-17 13:17:35
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,vivado和ise有很多
