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发表于 2016-1-19 20:51:04
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- module Test_USB2 (
- input clk,
- input reset,
- input wire i_u_flaga, //EP2 empty flag
- input wire i_u_flagd, //EP6 full flag
- input wire i_u_flagc,
- output reg o_u_slwr, //u_slwr#
- output reg o_u_slrd, //u_slrd#
- output reg o_u_sloe, //u_sloe#
- output wire o_u_ifclk,
- output wire [1:0] o_u_addr,
- output reg [15:0] o_data_out
- );
- reg [1:0] STATE;
- reg [15:0] count;
- wire clk_24M;
- wire clk_12M;
- wire clk_4M;
- wire clk_48M;
- parameter IDLE = 2'h0;
- parameter WRITE_LOW16 = 2'h1;
- parameter WRITE_HIGH_16 = 2'h2;
- pll pll_inst (
- .inclk0 ( clk ), //clk_24M
- .c0 ( clk_24M ), //clk_24M
- .c1 ( clk_12M ), //clk_12M
- .c2 ( clk_4M ) , //clk_4M
- .c3 ( clk_48M )
- );
- assign o_u_addr = 2'b10; //选择FIFO端点6
- assign o_u_ifclk = clk_48M;
- // 数据源,用于验证USB与fpga通信
- always@(posedge clk_48M or negedge reset)
- begin
- if(!reset)
- count <= 16'h0;
- else
- count <= count+1;
- end
- // USB控制信号
- always@(posedge o_u_ifclk or negedge reset)
- begin
- if(!reset)
- begin
- o_data_out<=16'b0;
- o_u_slwr <= 1'b1;
- o_u_slrd <= 1'b1;
- o_u_sloe <= 1'b1;
- end
- else if(i_u_flagd== 1'b1)
- begin
- o_u_slwr <= 1'b0;
- o_data_out<= count;
- end
- else
- o_u_slwr <= 1'b1;
- end
- endmodule
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