求助,看看这段Verilog有什么问题,
module rx_flame(input clk,
input rdsig, //串口接收数据有效信号
input rxdata, //串口接收数据
output ledctr //LED控制
);
reg sync_state = 4'h0;
reg rxcounter = 8'h0;//接收字符串计数
reg ledctr = 4'hf;
reg rxstore; //存储接受字符
//--------------internal signal declarration----------
parameter IDLE=4'h0,
SYNC_HEAD=4'h1,
LAOD_DATA_0=4'h2,
LAOD_DATA_1=4'h3,
SYNC_END=4'h4;
always@(posedge clk)
case (sync_state)
IDLE:
begin
ledctr <= 4'b1111;
rxcounter <= 4'h0;
end
SYNC_HEAD:
begin
if(rxstore == 8'hb1) //加上这一行就报错.
ledctr <= 4'b1110;
end
LAOD_DATA_0:
begin
;
end
SYNC_END:
begin
ledctr <= 4'h0;
end
default: ;
endcase
always@(posedge clk)
if(rdsig)
case(sync_state)
IDLE:if(rxdata == 8'hee )
sync_state <= SYNC_HEAD;
SYNC_HEAD:
if(rxdata == 8'hff )
sync_state <= SYNC_END;
else
begin
if(rxcounter == 0)
begin
rxstore <=rxdata;
rxcounter <= rxcounter+ 1'b1;
end
else if(rxcounter == 1)
begin
rxstore <=rxdata;
rxcounter <= rxcounter+ 1'b1;
end
else ;
end
SYNC_END: ;
default:;
endcase
else ;
endmodule
加上这一行就报错,该怎么改?
报错信息是这个
Line 44: Signal rxcounter in unit rx_flame is connected to following multiple drivers: rxcounter一个信号只能在一个always语句块里面被驱动，你这个两个always语句块都有rxcounter被赋值的情况 cloudboy 发表于 2020-11-4 19:33
rxcounter一个信号只能在一个always语句块里面被驱动，你这个两个always语句块都有rxcounter被赋值的情况 ...
谢谢, 仔细一看,果然是你讲的.
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