【求助】FPGA的nCEO用作IO后其他复用管脚不设置为IO综合报错

xtaens

如题，fpga型号见下图，nCEO脚用作普通IO后，在复用管脚设置了作为IO用，其他管脚采用默认设置，综合报错，必须把其他复用管脚全部设置为用户IO则综合不报错了。
但是原子哥的有关SRAM例程中也使用了nCEO脚，设置中只把nCEO设置为IO，其他默认，综合就不报错，我的为什么就报错了呢，给位高手给解释下，谢谢

1、原子哥的原理图和nCEO设置



2、我的原理图和nCEO设置




3、我的综合报错信息


4、这样设置后综合通过




编辑原因：修改了排版

xtaens

这是4条错误提示信息：
Error (169187): Following feature(s) of I/O pin ~ALTERA_ASDO_DATA1~ has invalid setting(s) in the configuration scheme ACTIVE_SERIAL when the pin is placed at pin location 6
        Info (169189): I/O feature 'Weak Pull Up' has an invalid setting. The setting should be ON.
Error (169187): Following feature(s) of I/O pin ~ALTERA_FLASH_nCE_nCSO~ has invalid setting(s) in the configuration scheme ACTIVE_SERIAL when the pin is placed at pin location 8
        Info (169189): I/O feature 'Weak Pull Up' has an invalid setting. The setting should be ON.
Error (169187): Following feature(s) of I/O pin ~ALTERA_DCLK~ has invalid setting(s) in the configuration scheme ACTIVE_SERIAL when the pin is placed at pin location 12
        Info (169189): I/O feature 'Weak Pull Up' has an invalid setting. The setting should be ON.
Error (169187): Following feature(s) of I/O pin ~ALTERA_DATA0~ has invalid setting(s) in the configuration scheme ACTIVE_SERIAL when the pin is placed at pin location 13
        Info (169189): I/O feature 'Weak Pull Up' has an invalid setting. The setting should be ON.

xtaens

进度信息：

xtaens

zxq6 发表于 2019-10-26 20:00
用了vivado后，真怀念quartus的编译速度。

嗯，一般的电脑编译一个小工程60秒左右，真的很快。。。以前用ISE，一个流水灯都要编译好几分钟

xtaens

问题已经解决，，这个是编译器的bug问题。要么升级编译器（我用13.0），可以升级到13.1或者更高；要么按照官方给的方法屏蔽psf文件中下面一行语句即可

set_global_assignment -name WEAK_PULL_UP_RESISTOR OFF

官方解释：

https://www.intel.com/content/ww ... rd04072014_413.html