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发表于 2020-7-17 20:33:48
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xilinx的器件一般要动态调整采样相位，它每个版本编译出来的延迟是不定的（我曾经遇到这个问题，xinlin FAE也未解决），之后就再也不用固定延迟了，IDELAYE用
法很简单，给你个例子,输入数据是datain_p，输入时钟inclock_p，最终输出数据为dataout_h，dataout_l；你调整value_in这个参数，然后去检测你的同步头是否能采集稳定
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uIDELAYE : IDELAYE3
generic map (
CASCADE => "NONE" , -- Cascade setting (MASTER, NONE, SLAVE_END, SLAVE_MIDDLE)
DELAY_FORMAT => "COUNT" , -- Units of the DELAY_VALUE (COUNT, TIME)
DELAY_SRC => "IDATAIN" , -- Delay input (IDATAIN, DATAIN)
DELAY_TYPE => "VAR_LOAD" , -- FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
DELAY_VALUE => 0 , -- Input delay tap setting (0-31)
IS_CLK_INVERTED => '0' , -- Optional inversion for CLK
IS_RST_INVERTED => '0' , -- Optional inversion for RST
REFCLK_FREQUENCY => 250.0 , -- IDELAYCTRL clock input frequency in MHz (200.0-2667.0)
SIM_DEVICE => "ULTRASCALE_PLUS" ,-- Set the device version (ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1,ULTRASCALE_PLUS_ES2)
UPDATE_MODE => "ASYNC" -- Determines when updates to the delay will take effect (ASYNC, MANUAL,SYNC)
)
port map (
CASC_OUT => open , -- 1-bit output: Cascade delay output to ODELAY input cascade
CNTVALUEOUT => open , -- 5-bit output: Counter value output
DATAOUT => dataout , -- 1-bit output: Delayed data output
CASC_IN => '0' , -- 1-bit input: Dynamic clock inversion input
CASC_RETURN => '0' , -- 1-bit input: Cascade delay returning from slave ODELAY DATAOUT
CE => '0' , -- 1-bit input: Active high enable increment/decrement input
CLK => inclock_p , -- 1-bit input: Clock input
CNTVALUEIN => value_in(8 downto 0) , -- 5-bit input: Counter value input
DATAIN => '0' , -- 1-bit input: Internal delay data input
EN_VTC => '0' , -- 1-bit input: Keep delay constant over VT
IDATAIN => datain_p , -- 1-bit input: Data input from the I/O
INC => '0' , -- 1-bit input: Increment / Decrement tap delay input
LOAD => '1',--load_in , -- 1-bit input: Load IDELAY_VALUE input
RST => '0' -- 1-bit input: Active-high reset tap-delay input
);
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uIDDR : IDDRE1
generic map (
DDR_CLK_EDGE => "OPPOSITE_EDGE", -- IDDRE1 mode (OPPOSITE_EDGE, SAME_EDGE, SAME_EDGE_PIPELINED)
IS_CB_INVERTED => '1', -- Optional inversion for CB
IS_C_INVERTED => '0') -- Optional inversion for C'
port map (
Q1 => dataout_h , -- 1-bit output: Registered parallel output 1
Q2 => dataout_l , -- 1-bit output: Registered parallel output 2
C => inclock_p , -- 1-bit input: High-speed clock
CB => inclock_p , -- 1-bit input: Inversion of High-speed clock C
D => dataout , -- 1-bit input: Serial Data Input
R => '0' -- 1-bit input: Active High Async Reset
); |
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楼主
，用iddr的话，调延时跟用iserdes原理一样吗？
，很感兴趣.....
