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昨天几乎一晚没睡,参考了很多代码,现在只是点亮了,没进行美化,我是新手,大家别拍砖,呵呵。
module vga(
clock,
switch,
disp_RGB,
hsync,
vsync
);
input clock; //系统输入时钟
input [1:0]switch;
output [2:0]disp_RGB; //VGA数据输出
//disp_RGB[0]:蓝
//disp_RGB[1]:红
//disp_RGB[2]:绿
output hsync; //VGA行同步信号
output vsync; //VGA场同步信号
reg [11:0] hcount; //VGA行扫描计数器
reg [11:0] vcount; //VGA场扫描计数器
reg [2:0] data;
reg [2:0] h_dat;
reg [2:0] v_dat;
wire dat_act;
wire hsync;
wire vsync;
//VGA行、场扫描时序参数表
parameter //1024*768@60Hz//65M
h_Front_porch = 12'd24,
h_Sync_pulse = 12'd136,
h_Back_porch = 12'd160,
Whole_line = 12'd1344,
v_Front_porch = 12'd3,
v_Sync_pulse = 12'd6,
v_Back_porch = 12'd29,
Whole_frame = 12'd806;
//************************VGA驱动部分*******************************
//行场扫描
//行扫描 hcount 从0开始计数到 Whole_line
//场扫描 vcount 从0开始计数到 Whole_frame
always @(posedge clock)
begin
// if (hcount == Whole_line) //行扫描计数到Whole line
if (hcount == 12'd1344) //行扫描计数到Whole line
begin
hcount <= 1'd0;
// if (vcount == Whole_frame) //场扫描计数到Whole frame
if (vcount == 12'd806) //场扫描计数到Whole frame
vcount <= 1'd0;
else
vcount <= vcount + 1'd1;
end
else
begin
hcount <= (hcount + 1'd1);
end
end
//同步信号输出
reg hsync_r,vsync_r;
always @(posedge clock)
begin
hsync_r <= (hcount > h_Sync_pulse);
vsync_r <= (vcount > v_Sync_pulse);
end
assign hsync = hsync_r;//产生行同步信号(低电平)
assign vsync = vsync_r;//产生场同步信号(低电平)
//数据输出
assign dat_act = ((hcount >= (h_Sync_pulse + h_Back_porch)) && (hcount < (Whole_line - h_Front_porch)))
&& ((vcount >= (v_Sync_pulse + v_Back_porch)) && (vcount < (Whole_frame - v_Front_porch)));
assign disp_RGB = (dat_act) ? data : 3'h00;
//************************显示数据处理部分*******************************
always @(posedge clock)
begin
case(switch[1:0])
2'd0: data <= h_dat; //选择横彩条
2'd1: data <= v_dat; //选择竖彩条
2'd2: data <= (v_dat ^ h_dat); //产生棋盘格
2'd3: data <= (v_dat ~^ h_dat); //产生棋盘格
endcase
end
always @(posedge clock) //产生竖彩条
begin
if(hcount < 223)
v_dat <= 3'h7; //白
else if(hcount < 303)
v_dat <= 3'h6; //黄
else if(hcount < 383)
v_dat <= 3'h5; //青
else if(hcount < 463)
v_dat <= 3'h4; //绿
else if(hcount < 543)
v_dat <= 3'h3; //紫
else if(hcount < 623)
v_dat <= 3'h2; //红
else if(hcount < 703)
v_dat <= 3'h1; //蓝
else
v_dat <= 3'h0; //黑
end
always @(posedge clock) //产生横彩条
begin
if(vcount < 94)
h_dat <= 3'h7; //白
else if(vcount < 154)
h_dat <= 3'h6; //黄
else if(vcount < 214)
h_dat <= 3'h5; //青
else if(vcount < 274)
h_dat <= 3'h4; //绿
else if(vcount < 334)
h_dat <= 3'h3; //紫
else if(vcount < 394)
h_dat <= 3'h2; //红
else if(vcount < 454)
h_dat <= 3'h1; //蓝
else
h_dat <= 3'h0; //黑
end
endmodule
点击此处下载 ourdev_529077.rar(文件大小:1.07M) (原文件名:VGA_1024_768.rar)
顺便请教,参数定义parameter的使用,百思不解,请高手指点
程序中:
if (hcount == Whole_line) //判断hcount计数是否达到 Whole_line 的值
使用不正常,但是
if (hcount == 12'd1344) //判断hcount计数是否达到 Whole_line 的值
判断正常。
到底是什么原因呢??? |
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