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发表于 2017-1-22 12:37:15
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AM5728:
For Silicon Revision 1.1 information, see SPRS915
Dual ARM® Cortex®-A15 Microprocessor Subsystem
Up to 2 C66x™ Floating-Point VLIW DSP
Fully Object-Code Compatible With C67x™ and C64x+™
Up to Thirty-two 16 × 16-Bit Fixed-Point Multiplies per Cycle
Up to 2.5MB of On-Chip L3 RAM
Two DDR3/DDR3L Memory Interface (EMIF) Modules
Supports up to DDR3-1066
Up to 2GB Supported per EMIF
Dual ARM® Cortex®-M4 co-processors
IVA-HD Subsystem
Display Subsystem
Full-HD Video (1920 × 1080p, 60 fps)
Multiple Video Input and Video Output
2D and 3D Graphics
Display Controller With DMA Engine and up to Three Pipelines
HDMI™ Encoder: HDMI 1.4a and DVI 1.0 Compliant
2x Dual-Core Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS)
2D-Graphics Accelerator (BB2D) Subsystem
Vivante™ GC320 Core
Video Processing Engine (VPE)
Dual-Core PowerVR® SGX544™ 3D GPU
Crypto Hardware Accelerators
AES, SHA, RNG, DES and 3DES
Three Video Input Port (VIP) Modules
General-Purpose Memory Controller (GPMC)
Enhanced Direct Memory Access (EDMA) Controller
2-Port Gigabit Ethernet (GMAC)
Sixteen 32-Bit General-Purpose Timers
32-Bit MPU Watchdog Timer
Five Inter-Integrated Circuit (I2C) Ports
HDQ™/1-Wire® Interface
Ten Configurable UART/IrDA/CIR Modules
Four Multichannel Serial Peripheral Interfaces (McSPI)
Quad SPI Interface (QSPI)
SATA Gen2 Interface
Eight Multichannel Audio Serial Port (McASP) Modules
SuperSpeed USB 3.0 Dual-Role Device
High-Speed USB 2.0 Dual-Role Device
Four MultiMedia Card/Secure Digital/Secure Digital Input Output Interfaces (MMC/SD/SDIO)
PCI-Express® 3.0 Subsystems With Two 5-Gbps Lanes
One 2-lane Gen2-Compliant Port
or Two 1-lane Gen2-Compliant Ports
Dual Controller Area Network (DCAN) Modules
CAN 2.0B Protocol
Up to 247 General-Purpose I/O (GPIO) Pins
Power, Reset, and Clock Management
On-Chip Debug With CTools Technology
28-nm CMOS Technology
23 mm × 23 mm, 0.8-mm Pitch, 760-Pin BGA (ABC) |
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