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发表于 2012-5-12 16:08:27
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WWC 发表于 2012-5-10 17:53
顶楼上,比较业啊。
一般来讲SDRAM访问不正常(EMC NAND正常),都是SDRAM时序的问题。
官方的代码 ...
void Delay_ms(u32 dat)
{
TIM_Waitms(dat);
}
void EMC_GPIO_Init (void)
{
LPC_IOCON->P3_0 = (1<<0 | 1<<3 | 0<<5 | 1<<9); /* D0 @ P3.0 */
LPC_IOCON->P3_1 = (1<<0 | 1<<3 | 0<<5 | 1<<9); /* D1 @ P3.1 */
LPC_IOCON->P3_2 = (1<<0 | 0<<3 | 0<<5 | 1<<9); /* D2 @ P3.2 */
LPC_IOCON->P3_3 = (1<<0 | 1<<3 | 0<<5 | 1<<9); /* D3 @ P3.3 */
LPC_IOCON->P3_4 = (1<<0 | 1<<3 | 0<<5 | 1<<9); /* D4 @ P3.4 */
LPC_IOCON->P3_5 = (1<<0 | 1<<3 | 0<<5 | 1<<9); /* D5 @ P3.5 */
LPC_IOCON->P3_6 = (1<<0 | 1<<3 | 0<<5 | 1<<9); /* D6 @ P3.6 */
LPC_IOCON->P3_7 = (1<<0 | 1<<3 | 0<<5 | 1<<9); /* D7 @ P3.7 */
LPC_IOCON->P3_8 = (1<<0 | 1<<3 | 0<<5 | 1<<9); /* D8 @ P3.8 */
LPC_IOCON->P3_9 = (1<<0 | 1<<3 | 0<<5 | 1<<9); /* D9 @ P3.9 */
LPC_IOCON->P3_10 = (1<<0 | 0<<3 | 0<<5 | 1<<9); /* D10 @ P3.10 */
LPC_IOCON->P3_11 = (1<<0 | 1<<3 | 0<<5 | 1<<9); /* D11 @ P3.11 */
LPC_IOCON->P3_12 = (1<<0 | 1<<3 | 0<<5 | 1<<9); /* D12 @ P3.12 */
LPC_IOCON->P3_13 = (1<<0 | 1<<3 | 0<<5 | 1<<9); /* D13 @ P3.13 */
LPC_IOCON->P3_14 = (1<<0 | 1<<3 | 0<<5 | 1<<9); /* D14 @ P3.14 */
LPC_IOCON->P3_15 = (1<<0 | 1<<3 | 0<<5 | 1<<9); /* D15 @ P3.15 */
// LPC_IOCON->P3_16 = (1<<0 | 1<<3 | 0<<5 | 1<<9); /* D16 @ P3.16 */
LPC_IOCON->P4_0 = (1<<0 | 1<<3 | 0<<5 | 1<<9); /* A0 @ P4.0 */
LPC_IOCON->P4_1 = (1<<0 | 1<<3 | 0<<5 | 1<<9); /* A1 @ P4.1 */
LPC_IOCON->P4_2 = (1<<0 | 1<<3 | 0<<5 | 1<<9); /* A2 @ P4.2 */
LPC_IOCON->P4_3 = (1<<0 | 1<<3 | 0<<5 | 1<<9); /* A3 @ P4.3 */
LPC_IOCON->P4_4 = (1<<0 | 1<<3 | 0<<5 | 1<<9); /* A4 @ P4.4 */
LPC_IOCON->P4_5 = (1<<0 | 1<<3 | 0<<5 | 1<<9); /* A5 @ P4.5 */
LPC_IOCON->P4_6 = (1<<0 | 1<<3 | 0<<5 | 1<<9); /* A6 @ P4.6 */
LPC_IOCON->P4_7 = (1<<0 | 1<<3 | 0<<5 | 1<<9); /* A7 @ P4.7 */
LPC_IOCON->P4_8 = (1<<0 | 1<<3 | 0<<5 | 1<<9); /* A8 @ P4.8 */
LPC_IOCON->P4_9 = (1<<0 | 1<<3 | 0<<5 | 1<<9); /* A9 @ P4.9 */
LPC_IOCON->P4_10 = (1<<0 | 1<<3 | 0<<5 | 1<<9); /* A10 @ P4.10 */
LPC_IOCON->P4_11 = (1<<0 | 1<<3 | 0<<5 | 1<<9); /* A11 @ P4.11 */
LPC_IOCON->P4_12 = (1<<0 | 1<<3 | 0<<5 | 1<<9); /* A12 @ P4.12 */
LPC_IOCON->P4_13 = (1<<0 | 1<<3 | 0<<5 | 1<<9); /* A13 @ P4.13 */
LPC_IOCON->P4_14 = (1<<0 | 1<<3 | 0<<5 | 1<<9); /* A14 @ P4.14 */
LPC_IOCON->P4_15 = (1<<0 | 1<<3 | 0<<5 | 1<<9); /* A15 @ P4.15 */
LPC_IOCON->P4_16 = (1<<0 | 1<<3 | 0<<5 | 1<<9); /* A16 @ P4.16 */
LPC_IOCON->P4_17 = (1<<0 | 1<<3 | 0<<5 | 1<<9); /* A17 @ P4.17 */
LPC_IOCON->P4_18 = (1<<0 | 1<<3 | 0<<5 | 1<<9); /* A18 @ P4.18 */
LPC_IOCON->P4_19 = (1<<0 | 1<<3 | 0<<5 | 1<<9); /* A19 @ P4.19 */
LPC_IOCON->P4_20 = (1<<0 | 1<<3 | 0<<5 | 1<<9); /* A20 @ P4.20 */
LPC_IOCON->P4_21 = (1<<0 | 1<<3 | 0<<5 | 1<<9); /* A21 @ P4.21 */
//LPC_IOCON->P4_22 = (1<<0 | 0<<3 | 0<<5 | 1<<9); /* A22 @ P4.22 */
// LPC_IOCON->P4_23 = (1<<0 | 0<<3 | 0<<5 | 1<<9); /* A23 @ P4.23 */
LPC_IOCON->P4_25 = (1<<0 | 1<<3 | 0<<5 | 1<<9); /* WEN @ P4.25 */
#if 1
LPC_IOCON->P4_24 = (1<<0 | 1<<3 | 0<<5 | 1<<9); /* OEN @ P4.24 */
// LPC_IOCON->P4_26 = (1<<0 | 0<<3 | 0<<5 | 1<<9); /* BLSN[0] @ P4.26 */
// LPC_IOCON->P4_27 = (1<<0 | 0<<3 | 0<<5 | 1<<9); /* BLSN[1] @ P4.27 */
// LPC_IOCON->P4_28 = (1<<0 | 0<<3 | 0<<5 | 1<<9); /* BLSN[2] @ P4.28 */
// LPC_IOCON->P4_29 = (1<<0 | 0<<3 | 0<<5 | 1<<9); /* BLSN[3] @ P4.29 */
LPC_IOCON->P4_30 = (1<<0 | 1<<3 | 0<<5 | 1<<9); /* CSN[0] @ P4.30 */
// LPC_IOCON->P4_31 = (1<<0 | 0<<3 | 0<<5 | 1<<9); /* CSN[1] @ P4.31 */
//LPC_IOCON->P2_14 = (1<<0 | 0<<3 | 0<<5 | 1<<9); /* CSN[2] @ P2.14 */
// LPC_IOCON->P2_15 = (1<<0 | 0<<3 | 0<<5 | 1<<9); /* CSN[3] @ P2.15 */
#endif
#if 1
LPC_IOCON->P2_16 = (1<<0 | 1<<3 | 0<<5 | 1<<9); /* CASN @ P2.16 */
LPC_IOCON->P2_17 = (1<<0 | 1<<3 | 0<<5 | 1<<9); /* RASN @ P2.17 */
LPC_IOCON->P2_18 = (1<<0 | 1<<3 | 0<<5 | 1<<9); /* CLK[0] @ P2.18 */
// LPC_IOCON->P2_19 = (1<<0 | 0<<3 | 0<<5 | 1<<9); /* CLK[1] @ P2.19 */
LPC_IOCON->P2_20 = (1<<0 | 1<<3 | 0<<5 | 1<<9); /* DYCSN[0] @ P2.20 */
// LPC_IOCON->P2_21 = (1<<0 | 0<<3 | 0<<5 | 1<<9); /* DYCSN[1] @ P2.21 */
// LPC_IOCON->P2_22 = (1<<0 | 0<<3 | 0<<5 | 1<<9); /* DYCSN[2] @ P2.22 */
// LPC_IOCON->P2_23 = (1<<0 | 0<<3 | 0<<5 | 1<<9); /* DYCSN[3] @ P2.23 */
LPC_IOCON->P2_24 = (1<<0 | 1<<3 | 0<<5 | 1<<9); /* CKE[0] @ P2.24 */
// LPC_IOCON->P2_25 = (1<<0 | 0<<3 | 0<<5 | 1<<9); /* CKE[1] @ P2.25 */
// LPC_IOCON->P2_26 = (1<<0 | 0<<3 | 0<<5 | 1<<9); /* CKE[2] @ P2.26 */
// LPC_IOCON->P2_27 = (1<<0 | 0<<3 | 0<<5 | 1<<9); /* CKE[3] @ P2.27 */
LPC_IOCON->P2_28 = (1<<0 | 1<<3 | 0<<5 | 1<<9); /* DQM[0] @ P2.28 */
LPC_IOCON->P2_29 = (1<<0 | 1<<3 | 0<<5 | 1<<9); /* DQM[1] @ P2.29 */
// LPC_IOCON->P2_30 = (1<<0 | 0<<3 | 0<<5 | 1<<9); /* DQM[2] @ P2.30 */
// LPC_IOCON->P2_31 = (1<<0 | 0<<3 | 0<<5 | 1<<9); /* DQM[3] @ P2.31 */
#endif
}
void EMCInit(void)
{
EMC_GPIO_Init();
LPC_SC->PCONP |= 0x00000800;
LPC_SC->EMCDLYCTL = 0x00080806;
LPC_EMC->Control = 0x00000001;
LPC_EMC->Config = 0x00000000;
}
void SDRAMInit( void )
{
TIM_TIMERCFG_Type TIM_ConfigStruct;
static u16 i, dwtemp;
uint32_t mhz, nsPerClk;
uint16_t wtemp = wtemp;
u32 k;
/**************************************************************************
* Initialize EMC for NOR FLASH
**************************************************************************/
EMCInit();
Delay_ms(100);
mhz = SystemCoreClock / 1000000;
if (LPC_SC->EMCCLKSEL)
mhz >>= 1;
nsPerClk = 1000 / mhz;
LPC_EMC->DynamicRP = EMC_NS2CLK(20, nsPerClk); /* 20ns, */
LPC_EMC->DynamicRAS = EMC_NS2CLK(42, nsPerClk);//*/ 15; /* 42ns to 100K ns, */
LPC_EMC->DynamicSREX = 2 - 1; /* tSRE, 1clk, */
LPC_EMC->DynamicAPR = 2 - 1; /* Not found!!! Estimated as 2clk, */
LPC_EMC->DynamicDAL = EMC_NS2CLK(20, nsPerClk) + 2; /* tDAL = tRP + tDPL = 20ns + 2clk */
LPC_EMC->DynamicWR = 2 - 1; /* 2CLK, */
LPC_EMC->DynamicRC = EMC_NS2CLK(63, nsPerClk); /* H57V2562GTR-75C tRC=63ns(min)*/
LPC_EMC->DynamicRFC = EMC_NS2CLK(63, nsPerClk); /* H57V2562GTR-75C tRFC=tRC */
LPC_EMC->DynamicXSR = EMC_NS2CLK(80, nsPerClk);//0x0000000F; /* exit self-refresh to active, 不知道,设为最久 */
LPC_EMC->DynamicRRD = EMC_NS2CLK(15, nsPerClk); /* 3clk, tRRD=15ns(min) */
LPC_EMC->DynamicMRD = 2 - 1; /* 2clk, tMRD=2clk(min) */
LPC_EMC->DynamicReadConfig = 0x00000001; /* Command delayed strategy, using EMCCLKDELAY */
LPC_EMC->DynamicRasCas0 = MDKCFG_RASCAS0VAL;
//Configure memory layout, but MUST DISABLE BUFFERs during configuration
LPC_EMC->DynamicConfig0 = 0x00001280;
Delay_ms(100); /* wait 100ms */
LPC_EMC->DynamicControl = 0x00000183; /* Issue NOP command */
Delay_ms(200); /* wait 200ms */
LPC_EMC->DynamicControl = 0x00000103; /* Issue PALL command */
LPC_EMC->DynamicRefresh = 4; /* ( n * 16 ) -> 32 clock cycles */
Delay_ms(200); /* wait 128 AHB clock cycles */
/* 64ms/4096=15.625us, nx16x8.33ns<15.625us, n<117.2*/
wtemp = 64000000 / (1 << 12);
wtemp -= 16;
wtemp >>= 4;
wtemp = wtemp * mhz / 1000;
LPC_EMC->DynamicRefresh = wtemp;
Delay_ms(200);
LPC_EMC->DynamicControl = 0x00000083; /* Issue MODE command */
//Timing for 48/60/72MHZ Bus
dwtemp = *((volatile uint16_t *)(SDRAM_BASE_ADDR | (0x33<<12))); /* 4 burst, 2 CAS latency */
Delay_ms(20);
LPC_EMC->DynamicControl = 0x00000000; /* Issue NORMAL command */
//[re]enable buffers
LPC_EMC->DynamicConfig0 |= 0x00080000;
Delay_ms(100); (100);
return;
} |
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