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发表于 2012-7-18 13:57:46
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Table 19. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 01
CL = 30 pF, Tamb = 40 C to 85 C, VDD(REG)(3V3) = 3.0 V to 3.6 V. All programmable delays EMCDLYCTL are bypassed.
Values guaranteed by design.
Symbol Parameter Conditions Min Typ Max Unit
Common to read and write cycles
Tcy(clk) clock cycle time [1] 12.5 - - ns
td(SV) chip select valid delay time 2.7 4.1 6.0 ns
th(S) chip select hold time 1.0 1.6 3.1 ns
td(RASV) row address strobe valid delay time 2.7 4.1 6.0 ns
th(RAS) row address strobe hold time 1.1 1.7 3.3 ns
td(CASV) column address strobe valid delay time 2.7 4.1 6.1 ns
th(CAS) column address strobe hold time 1.2 1.8 3.3 ns
td(WV) write valid delay time 3.2 4.8 7.1 ns
th(W) write hold time 1.6 2.3 4.2 ns
td(AV) address valid delay time 3.3 4.9 7.3 ns
th(A) address hold time 1.0 1.6 2.8 ns
Read cycle parameters
tsu(D) data input set-up time [2] 5.3 3.8 1.5 ns
th(D) data input hold time [3] 3.7 4.3 5.2 ns
Write cycle parameters
td(QV) data output valid delay time 3.3 4.9 7.3 ns
th(Q) data output hold time 0.2 0.5 1.6 ns |
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