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发表于 2013-8-21 21:11:13
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祥子 发表于 2013-8-21 20:59
AD的采样触发选择定时器的输出,把代码上传上来
#include <msp430.h>
#include "24l01.h"
#include "stdio.h"
#include "msp430_config.h"
volatile unsigned int results[6][15];
float X1, X2, Y1, Y2, Z1, Z2;
char s[32];
int main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
P6SEL = 0x4f; // Enable A/D channel inputs
ADC12CTL0 = ADC12ON+ADC12MSC+ADC12SHT0_15; // Turn on ADC12_A, extend sampling time
// to avoid overflow of results
ADC12MCTL0 = ADC12SREF_2; // Vr+ = VeREF+ (ext) and Vr-=AVss
ADC12CTL1 = ADC12SHP+ADC12CONSEQ_3+ADC12SHS0; // Use sampling timer, repeated sequence
// ADC12CTL1 = ADC12SHP+ADC12CONSEQ_3;
ADC12MCTL0 = ADC12INCH_3; // ref+=AVcc, channel = A3
ADC12MCTL1 = ADC12INCH_6; // ref+=AVcc, channel = A6
ADC12MCTL2 = ADC12INCH_7; // ref+=AVcc, channel = A7
ADC12MCTL3 = ADC12INCH_2; // ref+=AVcc, channel = A2
ADC12MCTL4 = ADC12INCH_1; // ref+=AVcc, channel = A1
ADC12MCTL5 = ADC12INCH_0+ADC12EOS; // ref+=AVcc, channel = A0, end seq.
ADC12IE = 0x01; // Enable ADC12IFG.3
ADC12CTL0 |= ADC12ENC; // Enable conversions
// ADC12CTL0 |= ADC12SC;
spi_config();
while(NRF24L01_Check()) //
{
__delay_cycles(750); // 75 us delay @ ~1MHz
}
NRF24L01_TX_Mode();
NRF24L01_TxPacket("NRF24L01 is OK\r\n");
TA1CCR0 = 30;
TA1CCTL0 = CCIE; // CCR0 interrupt enabled
TA1CTL = TASSEL_1 + MC_1 + TACLR; // SMCLK, contmode, clear TAR
TA1CCTL1 = OUTMOD_4; // Toggle on EQU1 (TAR = 0)
TA1CTL = TASSEL_1 + MC_1;
__bis_SR_register(LPM3_bits + GIE); // Enter LPM0, Enable interrupts
__no_operation(); // For debugger
}
#pragma vector=ADC12_VECTOR
__interrupt void ADC12ISR (void)
{
static unsigned int index = 0;
switch(__even_in_range(ADC12IV,34))
{
case 0: break; // Vector 0: No interrupt
case 2: break; // Vector 2: ADC overflow
case 4: break; // Vector 4: ADC timing overflow
case 6:
results[0][index] = ADC12MEM0; // Move A0 results, IFG is cleared
results[1][index] = ADC12MEM1; // Move A1 results, IFG is cleared
results[2][index] = ADC12MEM2; // Move A2 results, IFG is cleared
results[3][index] = ADC12MEM3; // Move A0 results, IFG is cleared
results[4][index] = ADC12MEM4; // Move A1 results, IFG is cleared
results[5][index] = ADC12MEM5; // Move A2 results, IFG is cleared
index++; // Increment results index, modulo; Set Breakpoint1 here
if (index == 6)
{
X1 = ((float)results[0][5]/4096)*2800;
Y1 = ((float)results[1][5]/4096)*2800;
Z1 = ((float)results[2][5]/4096)*2800;
X2 = ((float)results[3][5]/4096)*2800;
Y2 = ((float)results[4][5]/4096)*2800;
Z2 = ((float)results[5][5]/4096)*2800;
sprintf((char *)s,"%.0f@%.0f@%.0f@%.0f@%.0f@%.0f\r\n", Z2, Z1, Y2, Y1, X2, X1);
if(NRF24L01_TxPacket(s) == 0x20)
{
//__delay_cycles(750); // 75 us delay @ ~1MHz
}else
{
};
index = 0; // Reset index, Set breakpoint 2 here
}
// Vector 6: ADC12IFG0
case 8: break; // Vector 8: ADC12IFG1
case 10: break; // Vector 10: ADC12IFG2
case 12: break; // Vector 12: ADC12IFG3
case 14: break; // Vector 14: ADC12IFG4
case 16: break; // Vector 16: ADC12IFG5
case 18: break; // Vector 18: ADC12IFG6
case 20: break; // Vector 20: ADC12IFG7
case 22: break; // Vector 22: ADC12IFG8
case 24: break; // Vector 24: ADC12IFG9
case 26: break; // Vector 26: ADC12IFG10
case 28: break; // Vector 28: ADC12IFG11
case 30: break; // Vector 30: ADC12IFG12
case 32: break; // Vector 32: ADC12IFG13
case 34: break; // Vector 34: ADC12IFG14
default: break;
}
}
// Timer A0 interrupt service routine
#pragma vector=TIMER1_A0_VECTOR
__interrupt void TIMER1_A0_ISR(void)
{
} |
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