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发表于 2013-11-22 14:07:39
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本帖最后由 zhcj66 于 2013-11-22 14:08 编辑
- 通过HSE(8MHz)得到108MHz SysClk的配置过程：
- static void SetSysClockTo108(void)
- {
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CR & RCC_CR_HSERDY;
- StartUpCounter++;
- } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
- if (HSEStatus == (uint32_t)0x01)
- {
- /* HCLK = SYSCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-
- /* PCLK2 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-
- /* PCLK1 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
- /* PLL configuration: PLLCLK = HSE/2* (15+12) = 108 MHz */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
- RCC_CFGR_PLLMULL));
- RCC->CFGR |= (uint32_t)(0x08000000 | RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL12);
- /* Enable PLL */
- RCC->CR |= RCC_CR_PLLON;
- /* Wait till PLL is ready */
- while((RCC->CR & RCC_CR_PLLRDY) == 0)
- {
- }
-
- /* Select PLL as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
- {
- }
- }
- else
- { /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
- }
- 通过HSI(8MHz)得到108MHzSysClk的配置过程
- static void SetSysClockTo108(void)
- {
- /* HCLK = SYSCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
- /* PCLK2 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-
- /* PCLK1 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
- /* PLL configuration: PLLCLK = HSI/2* (15+12) = 108 MHz */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL));
- RCC->CFGR |= (uint32_t)(0x08000000 | RCC_CFGR_PLLSRC_HSI_Div2 | RCC_CFGR_PLLMULL12);
- /* Enable PLL */
- RCC->CR |= RCC_CR_PLLON;
- /* Wait till PLL is ready */
- while((RCC->CR & RCC_CR_PLLRDY) == 0)
- {
- }
-
- /* Select PLL as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
- {
- }
- }
- 如果使用串口
- 还应该修改 RCC_GetClocksFreq 函数，以获得正确的系统时钟，具体修改方法
- RCC_GetClocksFreq的修改：
- 先修改以下几个值：
- #define CFGR_PLL_Mask ((uint32_t)0xF7C0FFFF)
- #define CFGR_PLLMull_Mask ((uint32_t)0x083C0000)
- #define CFGR_ADCPRE_Reset_Mask ((uint32_t)0xEFFF3FFF)
- #define CFGR_ADCPRE_Set_Mask ((uint32_t)0x1000C000)
- static __I uint8_t ADCPrescTable[8] = {2, 4, 6, 8, 2, 12, 6, 16};
- 修改函数：
- void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
- {
- uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0;
- /* Get SYSCLK source -------------------------------------------------------*/
- tmp = RCC->CFGR & CFGR_SWS_Mask;
- switch (tmp)
- {
- case 0x00: /* HSI used as system clock */
- RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
- break;
- case 0x04: /* HSE used as system clock */
- RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
- break;
- case 0x08: /* PLL used as system clock */
- /* Get PLL clock source and multiplication factor ----------------------*/
- pllmull = RCC->CFGR & CFGR_PLLMull_Mask;
- pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;
- if(((pllmull)&(0x08000000)) != 0)
- pllmull = (((pllmull)&(0xF7FFFFFF)) >> 18) + 17;
- else
- pllmull = ( pllmull >> 18) +2;
- if (pllsource == 0x00)
- {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
- RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;
- }
- else
- {
- /* HSE selected as PLL clock entry */
- if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET)
- {/* HSE oscillator clock divided by 2 */
- RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull;
- }
- else
- {
- RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull;
- }
- }
- break;
- default:
- RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
- break;
- }
- /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
- /* Get HCLK prescaler */
- tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;
- tmp = tmp >> 4;
- presc = APBAHBPrescTable[tmp];
- /* HCLK clock frequency */
- RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
- /* Get PCLK1 prescaler */
- tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;
- tmp = tmp >> 8;
- presc = APBAHBPrescTable[tmp];
- /* PCLK1 clock frequency */
- RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
- /* Get PCLK2 prescaler */
- tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;
- tmp = tmp >> 11;
- presc = APBAHBPrescTable[tmp];
- /* PCLK2 clock frequency */
- RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
- /* Get ADCCLK prescaler */
- tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;
- tmp = ((tmp >> 14)&&(0xF))+(tmp >> 26);
- presc = ADCPrescTable[tmp];
- /* ADCCLK clock frequency */
- RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
- }
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