Verilog写的一段简易CPU

Sendzimir · 发表于 2013-11-30 14:05:37

本帖最后由 Sendzimir 于 2013-11-30 14:13 编辑

module CPU(clk, led, segment, digit);
input clk;
// disable LEDs and 7 segment display
output [7:0] led;
output [7:0] segment;
output [8:0] digit;
assign segment[7:0] = 0;
assign digit[8:0] = 'hff;
// prescaler
reg [32:0] devide = 0;
reg [7:0] rLed = 0;
assign led = rLed;
`define INIT 1
`define EVALUATE 2
reg [15:0] ram [0:255]; // 256 words ram
reg [7:0] pc = 0; // program counter
reg [7:0] currentState = `INIT;
reg [7:0] nextState = `INIT;
reg [15:0] cmd;
reg [15:0] accu;
reg slowClock;
`define CMD_LED_ON 1
`define CMD_LED_OFF 2
`define CMD_LOAD_NEXT_TO_ACCU 3
`define CMD_WAIT_UNTIL_ACCU_IS_ZERO 4
`define CMD_JUMP_TO_ZERO 5
always @(posedge clk) begin
if (devide == 0) begin
devide <= 5000000;
slowClock <= ~slowClock;
end else devide <= devide - 1;
end
always @(posedge slowClock) begin
currentState = nextState;
case (currentState)
`INIT: begin
pc = 0; ram[pc] = `CMD_LED_ON;
pc = pc + 1; ram[pc] = `CMD_LOAD_NEXT_TO_ACCU;
pc = pc + 1; ram[pc] = 'h03; // 3 to accu
pc = pc + 1; ram[pc] = `CMD_WAIT_UNTIL_ACCU_IS_ZERO;
pc = pc + 1; ram[pc] = `CMD_LED_OFF;
pc = pc + 1; ram[pc] = `CMD_LOAD_NEXT_TO_ACCU;
pc = pc + 1; ram[pc] = 'h09; // 9 to accu
pc = pc + 1; ram[pc] = `CMD_WAIT_UNTIL_ACCU_IS_ZERO;
pc = pc + 1; ram[pc] = `CMD_JUMP_TO_ZERO;
pc = 0;
nextState = `EVALUATE;
end
`EVALUATE: begin
cmd = ram[pc];
pc = pc + 1;
case (cmd)
`CMD_LED_ON: rLed = 1;
`CMD_LED_OFF: rLed = 0;
`CMD_LOAD_NEXT_TO_ACCU: begin
accu = ram[pc];
pc = pc + 1;
end
`CMD_WAIT_UNTIL_ACCU_IS_ZERO: begin
if (accu != 0) begin
pc = pc - 1;
accu = accu - 1;
end
end
`CMD_JUMP_TO_ZERO: pc = 0;
endcase
end
endcase
end
always @(negedge slowClock) begin
currentState <= nextState;
end
endmodule

复制代码

Sendzimir · 发表于 2013-11-30 14:08:18

本帖最后由 Sendzimir 于 2013-11-30 14:16 编辑

用现有逻辑芯片搭建直接运行高级语言硬件
http://www.amobbs.com/forum.php?mod=viewthread&tid=5560754&page=1&extra=

Sendzimir · 发表于 2013-11-30 14:09:34

这段程序运行在Xilinx Spartan-3 Starter Kit，对Verilog不太了解，大家谁帮忙解释下上面这段程序。

cxhy · 发表于 2013-12-1 10:59:43

帮顶一顶

fsl · 发表于 2018-8-12 22:26:07

我是来学习的，谢谢楼主分享！

dongwang_fl · 发表于 2018-8-14 16:41:32

我是来学习的，谢谢楼主分享！

justdomyself · 发表于 2018-8-15 13:25:32

先预设好子命令然后状态机一条条的执行

unnormal · 发表于 2018-9-9 09:16:38

学习一下谢谢分享

qingyin2009 · 发表于 2018-9-9 10:02:22

lz帖子标题语意不明，看了回帖才知道你要干嘛

huangqi412 · 发表于 2018-9-9 20:23:46

写个求助会死

Verilog写的一段简易CPU

阿莫论坛20周年了！感谢大家的支持与爱护！！