手把手教你基于CyloneIVE系列FPGA芯片利用quartII软件生成RAM

cxhy

打开tools->MegaWizard Plug-In Manager 打开之后见图1。
   我们选第一个：新建


然后在第二个界面之后
右上角我们选择CyloneIV E芯片
语言选择Verilog HDL
在memary compiler下选择RAM：2-PORT,就是两个端口。在命名上面我们取名为dpram19200x16b.v
其中dp代表双端口 ram表示我们虚拟的目标。后面的19200x16b代表内存的深度和位宽。


好了，在基本的完成之后就开始正式的配置了。
在图三的界面下。我们选择第一个单端口输入单端口输出。第二个是两个端口既可以为输入也可以为输出。我们不选。
然后next

进入图4的界面考虑到不同的需求可以自由定制大小。这里考虑到我自己的情况。我选择深度我选择19200。下面的位宽我选择16位。在下面勾选M9K。
点击next

进入图5的界面
由于之前我们选择的是双端口。所以这里我们选择第二个：把读写时钟分离。其他的我们选择默认然后next

进入图6界面。什么都不动，直接next

这时候进入图7界面
这很重要。第一个选项是建立的RAM是空的。里面的字节是全零。第二个选项是把RAM内置初始数据。添加的数据必须是hex文件可以在Browse中选择。这里我选择一个图像的二进制文件
pic_1.hex

继续next进入图8

继续next进入图9
没得next了直接finish

然后就大功告成了。

cxhy

沙发自己坐。贴上生成的代码文件

// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram

// ============================================================
// File Name: dpram19200x16b.v
// Megafunction Name(s):
//                         altsyncram
//
// Simulation Library Files(s):
//                         altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 178 05/31/2012 SJ Full Version
// ************************************************************


//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors.  Please refer to the
//applicable agreement for further details.


// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module dpram19200x16b (
        data,
        rdaddress,
        rdclock,
        wraddress,
        wrclock,
        wren,
        q);

        input        [15:0]  data;
        input        [14:0]  rdaddress;
        input          rdclock;
        input        [14:0]  wraddress;
        input          wrclock;
        input          wren;
        output        [15:0]  q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
        tri1          wrclock;
        tri0          wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif

        wire [15:0] sub_wire0;
        wire [15:0] q = sub_wire0[15:0];

        altsyncram        altsyncram_component (
                                .address_a (wraddress),
                                .clock0 (wrclock),
                                .data_a (data),
                                .wren_a (wren),
                                .address_b (rdaddress),
                                .clock1 (rdclock),
                                .q_b (sub_wire0),
                                .aclr0 (1'b0),
                                .aclr1 (1'b0),
                                .addressstall_a (1'b0),
                                .addressstall_b (1'b0),
                                .byteena_a (1'b1),
                                .byteena_b (1'b1),
                                .clocken0 (1'b1),
                                .clocken1 (1'b1),
                                .clocken2 (1'b1),
                                .clocken3 (1'b1),
                                .data_b ({16{1'b1}}),
                                .eccstatus (),
                                .q_a (),
                                .rden_a (1'b1),
                                .rden_b (1'b1),
                                .wren_b (1'b0));
        defparam
                altsyncram_component.address_aclr_b = "NONE",
                altsyncram_component.address_reg_b = "CLOCK1",
                altsyncram_component.clock_enable_input_a = "BYPASS",
                altsyncram_component.clock_enable_input_b = "BYPASS",
                altsyncram_component.clock_enable_output_b = "BYPASS",
`ifdef NO_PLI
                altsyncram_component.init_file = "pic_1.rif"
`else
                altsyncram_component.init_file = "pic_1.hex"
`endif
,
                altsyncram_component.intended_device_family = "Cyclone IV E",
                altsyncram_component.lpm_type = "altsyncram",
                altsyncram_component.numwords_a = 19200,
                altsyncram_component.numwords_b = 19200,
                altsyncram_component.operation_mode = "DUAL_PORT",
                altsyncram_component.outdata_aclr_b = "NONE",
                altsyncram_component.outdata_reg_b = "CLOCK1",
                altsyncram_component.power_up_uninitialized = "FALSE",
                altsyncram_component.widthad_a = 15,
                altsyncram_component.widthad_b = 15,
                altsyncram_component.width_a = 16,
                altsyncram_component.width_b = 16,
                altsyncram_component.width_byteena_a = 1;


endmodule

// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "1"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "307200"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "pic_1.hex"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "pic_1.hex"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "19200"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "19200"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "15"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 15 0 INPUT NODEFVAL "rdaddress[14..0]"
// Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL "rdclock"
// Retrieval info: USED_PORT: wraddress 0 0 15 0 INPUT NODEFVAL "wraddress[14..0]"
// Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT VCC "wrclock"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 15 0 wraddress 0 0 15 0
// Retrieval info: CONNECT: @address_b 0 0 15 0 rdaddress 0 0 15 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 16 0 @q_b 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram19200x16b.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram19200x16b.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram19200x16b.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram19200x16b.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram19200x16b_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram19200x16b_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf

cxhy

下面是一些简单的介绍。来自网上
1 two_pram
位置：Symbol->megafunctions->storage->two_pram
功能：可以定制简单的双端口RAM。一个端口只能写，一个只能读，有独立的读写地址线。
特点：可以增加独立的读写时钟或输入输出时钟；可以定制不同的输入输出端口宽度；可以增加读使能信号。
2 altdpram
位置：Symbol->megafunctions->storage->altdpram
功能：可以定制简单的双端口RAM。一个端口只能写，一个只能读，有独立的读写地址线。
特点：可以增加独立的读写时钟或输入输出时钟；可以定制不同的输入输出端口宽度；可以增加读使能信号。
3 altsyncram
位置：Symbol->megafunctions->storage->altsyncram
功能：可以定制简单ROM,单口RAM,简单双口RAM,真正双口RAM。
特点：
4 dpram
位置：Symbol->megafunctions->storage->dpram
功能：可以定制简单双端口RAM,真正双口RAM。
特点：
5 csdpram
位置：Symbol->megafunctions->storage->csdpram
功能：Parameterized Cycle_shared Dual_port RAM。
特点：有busy信号
6 lpm_ram_dq
位置：Symbol->megafunctions->storage->lpm_ram_dq
功能：定制RAM。
特点：输入输出共用双向IO口,但地址线是两套独立,即数据输入时使用输入地址线,输出时使用输出地址线.
7 lpm_ram_dp
位置：Symbol->megafunctions->storage->lpm_ram_dp
功能：定制RAM。
特点：可以构建双端口RAM .
8 lpm_ram_io
位置：Symbol->megafunctions->storage->lpm_ram_io
功能：定制RAM。
特点：数据输入输出口为单一的IO口，共用一套地址线。与普通的RAM一样。

cxhy

最后感谢论坛里面无私帮助过我的人。

硬邦邦

谢谢分享,mark

zgxcom123

顶楼主！

QII自带的RAM IP还是很好用的哈~

蓝色风暴@FPGA

顶!!!!!!!

御风

这个很有用,顶楼主!

justin_n

我差点看成手把手教你生成ARM