一个sigma-delta ADC的滤波和抽取电路代码

RAMILE · 发表于 2016-2-1 16:03:55

本帖最后由 RAMILE 于 2016-2-1 16:15 编辑

代码是在AD7400的ds上面看的，ADI官方出品，非常简洁，滤波就是累加求平均

/*`Data is read on negative clk edge*/
module DEC256SINC24B(mdata1, mclk1, reset, DATA);
input mclk1; /*used to clk filter*/
input reset; /*used to reset filter*/
input mdata1; /*ip data to be filtered*/
output [15:0] DATA; /*filtered op*/
integer location;
integer info_file;
reg [23:0] ip_data1;
reg [23:0] acc1;
reg [23:0] acc2;
reg [23:0] acc3;
reg [23:0] acc3_d1;
reg [23:0] acc3_d2;
reg [23:0] diff1;
reg [23:0] diff2;
reg [23:0] diff3;
reg [23:0] diff1_d;
reg [23:0] diff2_d;
reg [15:0] DATA;
reg [7:0] word_count;
reg word_clk;
reg init;
/*Perform the Sinc ACTION*/
always @ (mdata1)
if(mdata1==0)
ip_data1 <= 0; /* change from a 0 to a -1 for 2's comp */
else
ip_data1 <= 1;
/*ACCUMULATOR (INTEGRATOR)
Perform the accumulation (IIR) at the speed
of the modulator.
Z = one sample delay
MCLKOUT = modulators conversion bit rate
*/
always @ (negedge mclk1 or posedge reset)
if (reset)
begin
/*initialize acc registers on reset*/
acc1 <= 0;
acc2 <= 0;
acc3 <= 0;
end
else
begin
/*perform accumulation process*/
acc1 <= acc1 + ip_data1;
acc2 <= acc2 + acc1;
acc3 <= acc3 + acc2;
end
/*DECIMATION STAGE (MCLKOUT/ WORD_CLK) */
always @ (posedge mclk1 or posedge reset)
if (reset)
word_count <= 0;
else
word_count <= word_count + 1;
always @ (word_count)
word_clk <= word_count[7];
/*DIFFERENTIATOR ( including decimation stage)
Perform the differentiation stage (FIR) at a
lower speed.
Z = one sample delay
WOR D_CLK = output word rate
*/
always @ (posedge word_clk or posedge reset)
if(reset)
begin
acc3_d2 <= 0;
diff1_d <= 0;
diff2_d <= 0;
diff1 <= 0;
diff2 <= 0;
diff3 <= 0;
end
else
begin
diff1 <= acc3 - acc3_d2;
diff2 <= diff1 - diff1_d;
diff3 <= diff2 - diff2_d;
acc3_d2 <= acc3;
diff1_d <= diff1;
diff2_d <= diff2;
end
/* Clock the Sinc output into an output
register
WORD_CLK = output word rate
*/
always @ (posedge word_clk)
begin
DATA[15] <= diff3[23];
DATA[14] <= diff3[22];
DATA[13] <= diff3[21];
DATA[12] <= diff3[20];
DATA[11] <= diff3[19];
DATA[10] <= diff3[18];
DATA[9] <= diff3[17];
DATA[8] <= diff3[16];
DATA[7] <= diff3[15];
DATA[6] <= diff3[14];
DATA[5] <= diff3[13];
DATA[4] <= diff3[12];
DATA[3] <= diff3[11];
DATA[2] <= diff3[10];
DATA[1] <= diff3[9];
DATA[0] <= diff3[8];
end
endmodule

复制代码

ljt80158015 · 发表于 2016-2-5 16:59:19

学习了

kevin_me · 发表于 2016-2-5 20:09:39

我项目上用的16位AD7606，芯片自带64倍过采样。相当于硬件帮你做64次求平均。等开年了，再把楼主的方法加进去看看效果。

agilityChen · 发表于 2016-2-5 20:39:44

可没有那么累加平均那么简单，这是个sinc3滤波器。

ersha4877 · 发表于 2016-2-5 21:16:46

谢谢，可能用的到

xwkm · 发表于 2016-3-7 18:24:41

这算法是个 sinc IIR滤波器 ,可不是什么累加求平均.

bangbangji · 发表于 2016-3-19 21:55:36

这个算法很经典，手册里还有图供理解，讲得很好，但是要理解需要一定数字滤波的基础。
这个是3阶的，改成其他阶数也好用。

DepravedLucien · 发表于 2016-4-8 10:40:07

学习了，谢谢

DepravedLucien · 发表于 2016-4-8 10:41:13

kevin_me 发表于 2016-2-5 20:09
我项目上用的16位AD7606，芯片自带64倍过采样。相当于硬件帮你做64次求平均。等开年了，再把楼主的方法加进 ...

如果用64倍过采样，那你AD7606的采样频率是多少，是不是只有200K/64?

advarx21ic · 发表于 2018-9-14 21:07:12

学习了，谢谢

gleam12315 · 发表于 2019-12-2 15:38:22

这代码以前从网上复制，说是ADC大赛需要用的。结果是从这里来的

一个sigma-delta ADC的滤波和抽取电路代码

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