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发表于 2019-6-18 11:55:21
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显示全部楼层
准备放弃了,怎么对照KEIL工程来设置,都不行,能改的都改了,贴一下我具体修改结果吧
1.修改文件\linux-cortexm-2.0.0\u-boot\board\stm\stm32f429-discovery\board.c
static const struct stm32f2_gpio_dsc ext_ram_fsmc_fmc_gpio[] = {
/* Chip is LQFP144, see DM00077036.pdf for details */
/* 79, FMC_D31 */
{STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_10},
/* 78, FMC_D30 */
{STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_9},
/* 77, FMC_D29 */
{STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_7},
/* 68, FMC_D28 */
{STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_6},
/* 67, FMC_D27 */
{STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_3},
/* 66, FMC_D26 */
{STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_2},
/* 65, FMC_D25 */
{STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_1},
/* 64, FMC_D24 */
{STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_0},
/* 63, FMC_D23 */
{STM32F2_GPIO_PORT_H, STM32F2_GPIO_PIN_15},
/* 60, FMC_D22 */
{STM32F2_GPIO_PORT_H, STM32F2_GPIO_PIN_14},
/* 59, FMC_D21 */
{STM32F2_GPIO_PORT_H, STM32F2_GPIO_PIN_13},
/* 58, FMC_D20 */
{STM32F2_GPIO_PORT_H, STM32F2_GPIO_PIN_12},
/* 115, FMC_D19 */
{STM32F2_GPIO_PORT_H, STM32F2_GPIO_PIN_11},
/* 114, FMC_D18 */
{STM32F2_GPIO_PORT_H, STM32F2_GPIO_PIN_10},
/* 86, FMC_D17 */
{STM32F2_GPIO_PORT_H, STM32F2_GPIO_PIN_9},
/* 85, FMC_D16 */
{STM32F2_GPIO_PORT_H, STM32F2_GPIO_PIN_8},
/* 79, FMC_D15 */
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_10},
/* 78, FMC_D14 */
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_9},
/* 77, FMC_D13 */
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_8},
/* 68, FMC_D12 */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_15},
/* 67, FMC_D11 */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_14},
/* 66, FMC_D10 */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_13},
/* 65, FMC_D9 */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_12},
/* 64, FMC_D8 */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_11},
/* 63, FMC_D7 */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_10},
/* 60, FMC_D6 */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_9},
/* 59, FMC_D5 */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_8},
/* 58, FMC_D4 */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_7},
/* 115, FMC_D3 */
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_1},
/* 114, FMC_D2 */
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_0},
/* 86, FMC_D1 */
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_15},
/* 85, FMC_D0 */
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_14},
/* 142, FMC_NBL3 */
{STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_5}, // edit
/* 141, FMC_NBL2 */
{STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_4}, // edit
/* 142, FMC_NBL1 */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_1},
/* 141, FMC_NBL0 */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_0},
/* 90, FMC_A15, BA1 */
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_5},
/* 89, FMC_A14, BA0 */
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_4},
/* K15, FMC_A13 */
/* 87, FMC_A12 */
// {STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_2},// edit
/* 57, FMC_A11 */
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_1}, //A11
/* 56, FMC_A10 */
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_0},
/* 55, FMC_A9 */
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_15},
/* 54, FMC_A8 */
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_14},
/* 53, FMC_A7 */
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_13},
/* 50, FMC_A6 */
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_12},
/* 15, FMC_A5 */
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_5},
/* 14, FMC_A4 */
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_4},
/* 13, FMC_A3 */
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_3},
/* 12, FMC_A2 */
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_2},
/* 11, FMC_A1 */
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_1},
/* 10, FMC_A0 */
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_0},
/* 136, SDRAM_NE */
//{STM32F2_GPIO_PORT_C, STM32F2_GPIO_PIN_2},
{STM32F2_GPIO_PORT_H, STM32F2_GPIO_PIN_6}, //SDNE1
//{STM32F2_GPIO_PORT_B, STM32F2_GPIO_PIN_6},
/* 49, SDRAM_NRAS */
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_11},
/* 132, SDRAM_NCAS */
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_15},
/* 26, SDRAM_NWE */
{STM32F2_GPIO_PORT_C, STM32F2_GPIO_PIN_0},
/* 135, SDRAM_CKE */
//{STM32F2_GPIO_PORT_C, STM32F2_GPIO_PIN_3},
{STM32F2_GPIO_PORT_H, STM32F2_GPIO_PIN_7}, //SDCKE1
//{STM32F2_GPIO_PORT_B, STM32F2_GPIO_PIN_5},
/* 93, SDRAM_CLK */
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_8},
};
/*
* Following are timings for MT48LC32M16A2, from corresponding datasheet
*/
#define SDRAM_CAS 3
#define SDRAM_NB 1 /* Number of banks */
#define SDRAM_MWID 2 //32 bit W9812G2GH-6
//#define SDRAM_MWID 1 /* 16 bit memory */
//#define SDRAM_NR 0x2 /* 13-bit row */
#define SDRAM_NR 0x1 /* 12-bit row */ // edit
//#define SDRAM_NC 0x2 /* 10-bit col */
#define SDRAM_NC 0x0 /* 8-bit col */ // edit
int dram_init(void)
{u32 temp,ix;
u32 freq;
int rv;
u32 *pAddr;
u32 i;
u32 temp1;
u32 temp2;
/*
* Enable FMC interface clock
*/
STM32_RCC->ahb3enr |= STM32_RCC_ENR_FMC;
/*
* Get frequency for NS2CLK calculation.
*/
freq = clock_get(CLOCK_HCLK) / CONFIG_SYS_RAM_FREQ_DIV;
printf("clock_get(CLOCK_HCLK) = %ld\n",clock_get(CLOCK_HCLK));
printf("freq = %d\n",freq);
temp1 = STM32_SDRAM_FMC->sdcr1;
temp1 &= ((u32)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID |
FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP |
FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
temp1 |= (u32)(CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT |
0 << FMC_SDCR_RPIPE_SHIFT |
1 << FMC_SDCR_RBURST_SHIFT );
STM32_SDRAM_FMC->sdcr1 = temp1;
printf("001 = 0X%08x\n",CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT |
SDRAM_CAS << FMC_SDCR_CAS_SHIFT |
SDRAM_NB << FMC_SDCR_NB_SHIFT |
SDRAM_MWID << FMC_SDCR_MWID_SHIFT |
SDRAM_NR << FMC_SDCR_NR_SHIFT |
SDRAM_NC << FMC_SDCR_NC_SHIFT |
0 << FMC_SDCR_RPIPE_SHIFT |
1 << FMC_SDCR_RBURST_SHIFT
);
temp2 = STM32_SDRAM_FMC->sdcr2;
temp2 &= ((u32)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID |
FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP |
FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
temp2 |= ((u32)(
// CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT |
SDRAM_CAS << FMC_SDCR_CAS_SHIFT |
SDRAM_NB << FMC_SDCR_NB_SHIFT |
SDRAM_MWID << FMC_SDCR_MWID_SHIFT |
SDRAM_NR << FMC_SDCR_NR_SHIFT |
SDRAM_NC << FMC_SDCR_NC_SHIFT
// SDRAM_NC << FMC_SDCR_NC_SHIFT |
// 0 << FMC_SDCR_RPIPE_SHIFT |
// 1 << FMC_SDCR_RBURST_SHIFT
));
STM32_SDRAM_FMC->sdcr2 = temp2;
printf("002---STM32_SDRAM_FMC->sdcr2 = %x\n",STM32_SDRAM_FMC->sdcr2);
temp1 = STM32_SDRAM_FMC->sdtr1;
temp1 &= ((u32)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS |
FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP |
FMC_SDTR1_TRCD));
temp1 |= ((u32)(
SDRAM_TRP << FMC_SDTR_TRP_SHIFT |
SDRAM_TRC << FMC_SDTR_TRC_SHIFT
));
STM32_SDRAM_FMC->sdtr1 = temp1;
printf("033 = 0X%08x\n",SDRAM_TRCD << FMC_SDTR_TRCD_SHIFT |
SDRAM_TRP << FMC_SDTR_TRP_SHIFT |
SDRAM_TWR << FMC_SDTR_TWR_SHIFT |
SDRAM_TRC << FMC_SDTR_TRC_SHIFT |
SDRAM_TRAS << FMC_SDTR_TRAS_SHIFT |
SDRAM_TXSR << FMC_SDTR_TXSR_SHIFT |
SDRAM_TMRD << FMC_SDTR_TMRD_SHIFT
);
temp2 = STM32_SDRAM_FMC->sdtr2;
temp2 &= ((u32)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS |
FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP |
FMC_SDTR1_TRCD));
temp2 |= ((u32)(
SDRAM_TRCD << FMC_SDTR_TRCD_SHIFT |
// SDRAM_TRP << FMC_SDTR_TRP_SHIFT |
SDRAM_TWR << FMC_SDTR_TWR_SHIFT |
// SDRAM_TRC << FMC_SDTR_TRC_SHIFT |
SDRAM_TRAS << FMC_SDTR_TRAS_SHIFT |
SDRAM_TXSR << FMC_SDTR_TXSR_SHIFT |
SDRAM_TMRD << FMC_SDTR_TMRD_SHIFT
));
STM32_SDRAM_FMC->sdtr2 = temp2;
printf("003---STM32_SDRAM_FMC->sdtr2 = %x\n",STM32_SDRAM_FMC->sdtr2);
//STM32_SDRAM_FMC->sdcmr = FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_START_CLOCK;
STM32_SDRAM_FMC->sdcmr = FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_START_CLOCK;
printf("004---STM32_SDRAM_FMC->sdcmr = %x\n",STM32_SDRAM_FMC->sdcmr);
udelay(200); /* 200 us delay, page 10, "Power-Up" */
FMC_BUSY_WAIT();
//STM32_SDRAM_FMC->sdcmr = FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_PRECHARGE;
STM32_SDRAM_FMC->sdcmr = FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_PRECHARGE;
printf("005---STM32_SDRAM_FMC->sdcmr = %x\n",STM32_SDRAM_FMC->sdcmr);
udelay(100);
FMC_BUSY_WAIT();
//STM32_SDRAM_FMC->sdcmr = (
// FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_AUTOREFRESH |
// 7 << FMC_SDCMR_NRFS_SHIFT
//);
STM32_SDRAM_FMC->sdcmr = (
FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_AUTOREFRESH |
7 << FMC_SDCMR_NRFS_SHIFT
);
printf("006---STM32_SDRAM_FMC->sdcmr = %x\n",STM32_SDRAM_FMC->sdcmr);
udelay(100);
FMC_BUSY_WAIT();
#define SDRAM_MODE_BL_SHIFT 0
#define SDRAM_MODE_CAS_SHIFT 4
#define SDRAM_MODE_WB_SHIFT 9
//#define SDRAM_MODE_BL 0
#define SDRAM_MODE_BL 1
#define SDRAM_MODE_CAS SDRAM_CAS
#define SDRAM_MODE_WB 1
//STM32_SDRAM_FMC->sdcmr = FMC_SDCMR_BANK_1 |
//(
// SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT |
// SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT
//) << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE;
printf("077 = 0X%08x\n",FMC_SDCMR_BANK_2 |
(
SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT |
SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT
// SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT |
// SDRAM_MODE_WB << SDRAM_MODE_WB_SHIFT
) << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE);
STM32_SDRAM_FMC->sdcmr = FMC_SDCMR_BANK_2 |
(
SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT |
SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT
// SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT |
// SDRAM_MODE_WB << SDRAM_MODE_WB_SHIFT
) << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE;
printf("007---STM32_SDRAM_FMC->sdcmr = %x\n",STM32_SDRAM_FMC->sdcmr);
udelay(100);
FMC_BUSY_WAIT();
//STM32_SDRAM_FMC->sdcmr = FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_NORMAL;
STM32_SDRAM_FMC->sdcmr = FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_NORMAL;
printf("008---STM32_SDRAM_FMC->sdcmr = %x\n",STM32_SDRAM_FMC->sdcmr);
FMC_BUSY_WAIT();
/* Refresh timer */
STM32_SDRAM_FMC->sdrtr = SDRAM_TREF;
printf("009---STM32_SDRAM_FMC->sdrtr = %x\n",STM32_SDRAM_FMC->sdrtr);
/*
* Fill in global info with description of SRAM configuration
*/
gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE;
gd->bd->bi_dram[0].size = CONFIG_SYS_RAM_SIZE;
rv = 0;
cortex_m3_mpu_full_access();
dram_initialized = 1;
pAddr = (u32 *)0xd0001000;
printf("pAddr = %x\n",(u32)pAddr);
for(i=0;i<32;i++) //32
{
*((u32 *)(pAddr +i)) = 0xAB000000+i;
printf("pAddr +%d = %x = %x\n",i,(u32)pAddr +i,*((u32 *)(pAddr +i)));
}
for(i=0;i<32;i++)
{
printf("*0x%08x -> i=%d\n",((u32)pAddr+i),i);
printf("*0x%08x = 0x%08x\n",(pAddr+i),*((u32 *)(pAddr +i)));
}
pAddr = (u32 *)0xd0001100;
for(i=0;i<8;i++)
{
*((u32 *)(pAddr +i)) = 0xAB000000+i;
printf("pAddr +%d = %x = %x\n",i,(u32)pAddr +i,*((u32 *)(pAddr +i)));
}
for(i=0;i<32;i++)
{
printf("*0x%08x -> i=%d\n",((u32)pAddr+i),i);
printf("*0x%08x = 0x%08x\n",((u32)pAddr+i),*((u32 *)(pAddr +i)));
}
return rv;
}
2.修改文件\linux-cortexm-2.0.0\u-boot\include\configs\stm32f429-discovery.h
#define CONFIG_NR_DRAM_BANKS 1
//#define CONFIG_NR_DRAM_BANKS 2
#define CONFIG_SYS_RAM_SIZE (16 * 1024 * 1024)
//#define CONFIG_SYS_RAM_SIZE (4 * 1024 * 1024)
#define CONFIG_SYS_RAM_CS 1
#define CONFIG_SYS_RAM_FREQ_DIV 2
//#define CONFIG_SYS_RAM_BASE 0xC0000000
#define CONFIG_SYS_RAM_BASE 0xD0000000
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