TMS32 F28335 CAN采样点设置问题

xofun

我在使用F28835 ECAN时想改下采样点，但是按照手册上的方法改，无论怎么改采样点一直为60%左右，测试方法是用CAN stress 注入干扰，哪位大神能帮我指点一下到底是程序问题还是测试方法问题？

程序如下，时钟为120M，波特率 500k

oid InitECana(void)        // Initialise eCAN-A module
{
/* Create a shadow register structure for the CAN control registers. This is
needed, since only 32-bit access is allowed to these registers. 16-bit access
to these registers could potentially corrupt the register contents or return
false data. This is especially true while writing to/reading from a bit
(or group of bits) among bits 16 - 31 */

    struct ECAN_REGS ECanaShadow;

    EALLOW;        // EALLOW enables access to protected bits

/* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/
    ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all;
    ECanaShadow.CANTIOC.bit.TXFUNC = 1;        // The CANTX pin is used for the CAN transmit functions
    ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all;
     
    ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all;
    ECanaShadow.CANRIOC.bit.RXFUNC = 1; //The CANRX pin is used for the CAN receive functions
    ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all;

/* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */
    // HECC mode also enables time-stamping feature

    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
    ECanaShadow.CANMC.bit.SCB = 1;        //select eCAN mode
    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;

  // turn on Auto Bus On to automatically get out of BUS OFF condition when things clear
    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
    ECanaShadow.CANMC.bit.ABO = 0;
    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;

/* Initialize all bits of 'Master Control Field' to zero */
// Some bits of MSGCTRL register come up in an unknown state. For proper operation,
// all bits (including reserved bits) of MSGCTRL must be initialized to zero

    ECanaMboxes.MBOX0.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX1.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX2.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX3.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX4.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX5.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX6.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX7.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX8.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX9.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX10.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX11.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX12.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX13.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX14.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX15.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX16.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX17.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX18.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX19.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX20.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX21.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX22.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX23.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX24.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX25.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX26.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX27.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX28.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX29.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX30.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX31.MSGCTRL.all = 0x00000000;

// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
//    as a matter of precaution.

    ECanaRegs.CANTA.all    = 0xFFFFFFFF;    /* Clear all TAn bits */

    ECanaRegs.CANRMP.all = 0xFFFFFFFF;    /* Clear all RMPn bits */

    ECanaRegs.CANGIF0.all = 0xFFFFFFFF;    /* Clear all interrupt flag bits */
    ECanaRegs.CANGIF1.all = 0xFFFFFFFF;


/* Configure bit timing parameters for eCANA*/        //Initialization sequence
    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
    ECanaShadow.CANMC.bit.CCR = 1 ;            // Set CCR = 1 (Configuration mode requested)
    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;

    ECanaShadow.CANES.all = ECanaRegs.CANES.all;
    // Wait for configuration mode
    do
    {
        ECanaShadow.CANES.all = ECanaRegs.CANES.all;
    } while(ECanaShadow.CANES.bit.CCE != 1 );          // Wait for CCE bit to be set..
    //now configuration mode active (CCR=1, CCE=1)

    ECanaShadow.CANBTC.all = 0;

    /* The following block for all 150 MHz SYSCLKOUT (75 MHz CAN clock) - default. Bit rate = 1 Mbps
    See Note at End of File */
    // BT = (TSEG1REG+1) + (TSEG2REG+1) + 1 = Total number of Tq per bit.
    // Bit rate = SYSCLKOUT / ((BRPREG+1) * BT)
//    ECanaShadow.CANBTC.bit.BRPREG = 19;     // 250kpbs 150 MHz SYSCLKOUT

/*           if(HCU_COM_BRD == BRD_250kpa)
        {
                ECanaShadow.CANBTC.bit.BRPREG = 15;
                   ECanaShadow.CANBTC.bit.TSEG2REG = 2;//3          
        }
        else if(HCU_COM_BRD == BRD_125kpa)
        {
                ECanaShadow.CANBTC.bit.BRPREG = 23;
                ECanaShadow.CANBTC.bit.TSEG2REG = 7;//3   
        }
        else*/
        {
                ECanaShadow.CANBTC.bit.BRPREG = 7;
                   ECanaShadow.CANBTC.bit.TSEG2REG = 2;//3          
        }
                ECanaShadow.CANBTC.bit.TSEG1REG = 10;
                        ECanaShadow.CANBTC.bit.SJWREG = 3;                        //Sync Jump width = 4 Tq

    ECanaShadow.CANBTC.bit.SAM = 1;
    ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all;

    //Nomral mode requested
    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
    ECanaShadow.CANMC.bit.CCR = 0 ;            // Set CCR = 0
    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;

    ECanaShadow.CANES.all = ECanaRegs.CANES.all;
    //Wait for normal mode
    do
    {
        ECanaShadow.CANES.all = ECanaRegs.CANES.all;
    } while(ECanaShadow.CANES.bit.CCE != 0 );         // Wait for CCE bit to be  cleared..
    //Initialization complete (now Normal mode)

    /* Disable all Mailboxes  */
    ECanaRegs.CANME.all = 0;        // Required before writing the MSGIDs
    EDIS;
    ECANA_Configure_Interrupts();
}
CAN stress 设置为

守候幸福_1

用这个公式算下看：（(TSEG1REG+1)+1） /（(TSEG1REG+1) +(TSEG2REG+1) +1）