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发表于 2017-8-1 16:13:17
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本帖最后由 90999 于 2017-8-2 11:43 编辑
- assign XO =!XI;
- assign CLK_IN = XO; //XI XO 反相器接晶体
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- //三分频
- reg [1:0]q1,q2;
- wire q3;
- always @(posedge CLK_IN) //CLK_IN 是时钟
- case (q1)
- 0:q1<=1;
- 1:q1<=2;
- 2:q1<=0;
- default:q1<=0;
- endcase
-
- always @(negedge RXCK)
- case (q2)
- 0:q2<=1;
- 1:q2<=2;
- 2:q2<=0;
- default:q2<=0;
- endcase
- assign q3=q1|q2; //q3=CLK_IN/3 q3 = CLK_IN的1/3
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- //
- assign A= (1&&P)||( CLK_IN&&(!P) );
- reg [7:0]n100;
- reg B,C,D,E,P;
- always @ (posedge A or negedge RST) //RST ϽµÑظ´Î»£¬·ñÔòP=1»á¹Ø±ÕʱÖÓA
- begin
- if(!RST)
- begin
- n100=0;
- end
- else
- begin
- B=0;C=0;D=0;E=0;P=0;
- if(n100==9) B=1;
- if(n100==19) C=1;
- if(n100==29) D=1;
- if(n100==39) E=1;
- if(n100==99) P=1;
- end
- end
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- reg [7:0]m255
- always @( posedge ( (C||D)||(E||B) ) //任意CDEB都触发
- begin
- if(B) //B触发清零
- begin
- m255=0;
- end
- else
- begin
- m255=m255+1; //其他加一
- end
- end
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- wire [wire] ADD_INA; //地址A 低8位
- reg [7:0] ADD_OUTA;
- always @(posedge LATCH_ADD) //地址锁存
- begin
- ADD_OUTA = ADD_INA;
- end
- assign ADD_A = {ADD_H8A,ADD_INA}; //地址A = 高8位低8位
- wire [wire] DATA_INA; //数据A输入
- reg [7:0] DATA_OUTA; //数据A输出
- always @(posedge LATCH_DATA) //数据锁存
- begin
- DATA_OUTA= DATA_INA;
- end
- wire [wire] ADD_INB;
- reg [7:0] ADD_OUTB;
- always @(posedge LATCH_ADD)
- begin
- ADD_OUTB= ADD_INB;
- end
- assign ADD_B = {ADD_H8A,ADD_OUTB};
- wire [wire] DATA_INB;
- reg [7:0] DATA_OUTB;
- always @(posedge LatchDATA)
- begin
- DATA_OUTB = DATA_INB;
- end
- assign DATA_OUT = DATA_OUTA + DATA_OUTB; //数据 = 数据A+数据B
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- inout [7:0] JI, KI, JO, KO;
- wire H,I;
- assign JI =( H? JO :8'bZZZZZZZZ ); //74HC245
- assign JO =( H? 8'bZZZZZZZZ :JI );
- assign KI =( I? KO :8'bZZZZZZZZ );
- assign KO =( I? 8'bZZZZZZZZ :KI );
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