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求助:VHDL写的51总线代码,出现输出乱码错误,如何解决

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出0入55汤圆

发表于 2018-8-1 16:11:54 | 显示全部楼层 |阅读模式
如下图,在网上搞了一个51总线的VHDL代码,稍微改了一下,编译过了。运行可以,可是代码不健壮啊!现在问题如下:
1.如果单片机和CPLD同时上电,则完全没问题,
2.如果单片机分开上电,或者在运行过程中复位单片机,则输出乱码,也就是总线时序乱了,不能自动恢复
自己想的解决办法:
1.在ALE下降沿后置一个标志位,如果读写信号来了发现标志位没置位则忽略,反之则读数据和复位标志位,保证总线时序是先读地址再读数据。

奈何眼高手低,VHDL里不能在两个process里对同一个信号赋值!!!请教大神,这个标志位如何写~~


代码如下:
  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3. use IEEE.STD_LOGIC_ARITH.ALL;
  4. use IEEE.STD_LOGIC_UNSIGNED.ALL;

  5. entity bus_51 is
  6. port(
  7.         P0:                 inout STD_LOGIC_VECTOR(7 downto 0);
  8.         P2:                 in STD_LOGIC_VECTOR(5 downto 0);
  9.         ALE:                 in STD_LOGIC;
  10.         WR,RD:                 in STD_LOGIC;
  11.        
  12.         AUDBY:                 in STD_LOGIC;
  13.         KEY1:                  in STD_LOGIC_VECTOR(7 downto 0);
  14.         KEY2:                  in STD_LOGIC_VECTOR(7 downto 0);
  15.         S1:                           in STD_LOGIC_VECTOR(4 downto 0);
  16.         S2:                           in STD_LOGIC_VECTOR(4 downto 0);
  17.         H1:                           in STD_LOGIC_VECTOR(3 downto 0);
  18.         H2:                           in STD_LOGIC_VECTOR(3 downto 0);
  19.         COIN1:                 in STD_LOGIC_VECTOR(1 downto 0);
  20.         COIN2:                 in STD_LOGIC_VECTOR(1 downto 0);
  21.         MB_C:                  in STD_LOGIC_VECTOR(3 downto 0);
  22.         SW1:                   in STD_LOGIC_VECTOR(7 downto 0);
  23.         LCDBY1:                in STD_LOGIC;
  24.         LCDBY2:                in STD_LOGIC;
  25.         SP485BY1:        in STD_LOGIC;
  26.         SP485BY2:        in STD_LOGIC;
  27.        
  28.         LED0:           out STD_LOGIC_VECTOR(0 downto 0);
  29.         LEDA:           out STD_LOGIC_VECTOR(1 downto 0);
  30.         LEDB:           out STD_LOGIC_VECTOR(1 downto 0);
  31.         LED8:           out STD_LOGIC_VECTOR(7 downto 0);
  32.         LEDY:           out STD_LOGIC_VECTOR(3 downto 0);
  33.         SSR1:           out STD_LOGIC_VECTOR(0 downto 0);
  34.         SSR2:           out STD_LOGIC_VECTOR(0 downto 0);
  35.         SSL1:           out STD_LOGIC_VECTOR(0 downto 0);
  36.         SSL2:           out STD_LOGIC_VECTOR(0 downto 0);
  37.         MB_O:           out STD_LOGIC_VECTOR(3 downto 0);
  38.         ST1032:         out STD_LOGIC_VECTOR(3 downto 0);

  39.         SP485EN1_O:   out STD_LOGIC_VECTOR(0 downto 0);
  40.         SP485EN2_O:   out STD_LOGIC_VECTOR(0 downto 0)

  41.         );
  42. end bus_51;

  43. Architecture C51_FPGA_BUS of bus_51 is
  44.         signal C51_Addr16          :STD_LOGIC_VECTOR(15 downto 0);---16 bit address
  45.         signal WR_EN,RD_EN        :STD_LOGIC;-----WR/RD Enable
  46.        
  47.         ------------------------- INTPUT --------------------------------------------
  48.         signal REG_IN_AUDBY        :STD_LOGIC_VECTOR(7 downto 0) := "11111111"; ---internal Register input
  49.         signal REG_IN_WJA          :STD_LOGIC_VECTOR(7 downto 0) := "11111111"; ---internal Register input
  50.         signal REG_IN_WJB          :STD_LOGIC_VECTOR(7 downto 0) := "11111111"; ---internal Register input
  51.         signal REG_IN_S1           :STD_LOGIC_VECTOR(7 downto 0) := "11111111"; ---internal Register input
  52.         signal REG_IN_S2           :STD_LOGIC_VECTOR(7 downto 0) := "11111111"; ---internal Register input
  53.         signal REG_IN_H1           :STD_LOGIC_VECTOR(7 downto 0) := "11111111"; ---internal Register input
  54.         signal REG_IN_H2           :STD_LOGIC_VECTOR(7 downto 0) := "11111111"; ---internal Register input
  55.         signal REG_IN_COIN1        :STD_LOGIC_VECTOR(7 downto 0) := "11111111"; ---internal Register input
  56.         signal REG_IN_COIN2        :STD_LOGIC_VECTOR(7 downto 0) := "11111111"; ---internal Register input
  57.         signal REG_IN_MB        :STD_LOGIC_VECTOR(7 downto 0) := "11111111"; ---internal Register input
  58.         signal REG_IN_SW1        :STD_LOGIC_VECTOR(7 downto 0) := "11111111"; ---internal Register input
  59. --        signal REG_IN_SW2        :STD_LOGIC_VECTOR(7 downto 0) := "11111111"; ---internal Register input
  60.         signal REG_IN_LCDBY1:STD_LOGIC_VECTOR(7 downto 0) := "11111111"; ---internal Register input
  61.         signal REG_IN_LCDBY2:STD_LOGIC_VECTOR(7 downto 0) := "11111111"; ---internal Register input
  62.         signal REG_IN_485BY1:STD_LOGIC_VECTOR(7 downto 0) := "11111111"; ---internal Register input
  63.         signal REG_IN_485BY2:STD_LOGIC_VECTOR(7 downto 0) := "11111111"; ---internal Register input
  64.        
  65.         --------------------------- INTPUT OUTPUT -----------------------------------
  66.         signal REG_INOUT_LED0        :STD_LOGIC_VECTOR(7 downto 0) := "00000000"; ---internal Register input
  67.         signal REG_INOUT_LEDA        :STD_LOGIC_VECTOR(7 downto 0) := "00000000"; ---internal Register input
  68.         signal REG_INOUT_LEDB        :STD_LOGIC_VECTOR(7 downto 0) := "00000000"; ---internal Register input
  69.         signal REG_INOUT_LED8        :STD_LOGIC_VECTOR(7 downto 0) := "00000000"; ---internal Register input
  70.         signal REG_INOUT_LEDY        :STD_LOGIC_VECTOR(7 downto 0) := "00000000"; ---internal Register input
  71.         signal REG_INOUT_SSR1        :STD_LOGIC_VECTOR(7 downto 0) := "00000000"; ---internal Register input
  72.         signal REG_INOUT_SSR2        :STD_LOGIC_VECTOR(7 downto 0) := "00000000"; ---internal Register input
  73.         signal REG_INOUT_SSL1        :STD_LOGIC_VECTOR(7 downto 0) := "00000000"; ---internal Register input
  74.         signal REG_INOUT_SSL2        :STD_LOGIC_VECTOR(7 downto 0) := "00000000"; ---internal Register input
  75.         signal REG_INOUT_MB                :STD_LOGIC_VECTOR(7 downto 0) := "00000000"; ---internal Register input
  76.         signal REG_INOUT_485EN1        :STD_LOGIC_VECTOR(7 downto 0) := "00000000"; ---internal Register input
  77.         signal REG_INOUT_485EN2        :STD_LOGIC_VECTOR(7 downto 0) := "00000000"; ---internal Register input
  78. --        signal REG_INOUT_Z                :STD_LOGIC_VECTOR(7 downto 0) := "00000000"; ---internal Register input
  79. --        signal REG_INOUT_M                :STD_LOGIC_VECTOR(7 downto 0) := "00000000"; ---internal Register input
  80. --        signal REG_INOUT_N                :STD_LOGIC_VECTOR(7 downto 0) := "00000000"; ---internal Register input
  81.         signal REG_INOUT_1032        :STD_LOGIC_VECTOR(7 downto 0) := "00000000"; ---internal Register input
  82.        
  83.         -------------------------- ADDR INPUT -------------------------------------------
  84.         CONSTANT ADDR_IN_AUDIO        :STD_LOGIC_VECTOR(15 downto 0) := x"8000"; ---internal Register input
  85.         CONSTANT ADDR_IN_WJA          :STD_LOGIC_VECTOR(15 downto 0) := x"8001"; ---internal Register input
  86.         CONSTANT ADDR_IN_WJB          :STD_LOGIC_VECTOR(15 downto 0) := x"8002"; ---internal Register input
  87.         CONSTANT ADDR_IN_S1           :STD_LOGIC_VECTOR(15 downto 0) := x"8003"; ---internal Register input
  88.         CONSTANT ADDR_IN_S2           :STD_LOGIC_VECTOR(15 downto 0) := x"8004"; ---internal Register input
  89.         CONSTANT ADDR_IN_H1           :STD_LOGIC_VECTOR(15 downto 0) := x"8005"; ---internal Register input
  90.         CONSTANT ADDR_IN_H2           :STD_LOGIC_VECTOR(15 downto 0) := x"8006"; ---internal Register input
  91.         CONSTANT ADDR_IN_COIN1        :STD_LOGIC_VECTOR(15 downto 0) := x"8007"; ---internal Register input
  92.         CONSTANT ADDR_IN_COIN2        :STD_LOGIC_VECTOR(15 downto 0) := x"8008"; ---internal Register input
  93.         CONSTANT ADDR_IN_MB                :STD_LOGIC_VECTOR(15 downto 0) := x"8009"; ---internal Register input
  94.         CONSTANT ADDR_IN_SW1        :STD_LOGIC_VECTOR(15 downto 0) := x"800E"; ---internal Register input
  95.         CONSTANT ADDR_IN_SW2        :STD_LOGIC_VECTOR(15 downto 0) := x"800F"; ---internal Register input
  96.         CONSTANT ADDR_IN_LCDBY1        :STD_LOGIC_VECTOR(15 downto 0) := x"8010"; ---internal Register input
  97.         CONSTANT ADDR_IN_LCDBY2        :STD_LOGIC_VECTOR(15 downto 0) := x"8011"; ---internal Register input
  98.         CONSTANT ADDR_IN_485BY1        :STD_LOGIC_VECTOR(15 downto 0) := x"8012"; ---internal Register input
  99.         CONSTANT ADDR_IN_485BY2        :STD_LOGIC_VECTOR(15 downto 0) := x"8013"; ---internal Register input
  100.        
  101.         ---------------------------ADDR INTPUT OUTPUT -----------------------------------
  102.         CONSTANT ADDR_INOUT_LED0        :STD_LOGIC_VECTOR(15 downto 0) := x"8080"; ---internal Register input
  103.         CONSTANT ADDR_INOUT_LEDA        :STD_LOGIC_VECTOR(15 downto 0) := x"8081"; ---internal Register input
  104.         CONSTANT ADDR_INOUT_LEDB        :STD_LOGIC_VECTOR(15 downto 0) := x"8082"; ---internal Register input
  105.         CONSTANT ADDR_INOUT_LED8        :STD_LOGIC_VECTOR(15 downto 0) := x"8083"; ---internal Register input
  106.         CONSTANT ADDR_INOUT_LEDY        :STD_LOGIC_VECTOR(15 downto 0) := x"8084"; ---internal Register input
  107.         CONSTANT ADDR_INOUT_SSR1        :STD_LOGIC_VECTOR(15 downto 0) := x"8085"; ---internal Register input
  108.         CONSTANT ADDR_INOUT_SSR2        :STD_LOGIC_VECTOR(15 downto 0) := x"8086"; ---internal Register input
  109.         CONSTANT ADDR_INOUT_SSL1        :STD_LOGIC_VECTOR(15 downto 0) := x"8087"; ---internal Register input
  110.         CONSTANT ADDR_INOUT_SSL2        :STD_LOGIC_VECTOR(15 downto 0) := x"8088"; ---internal Register input
  111.         CONSTANT ADDR_INOUT_MB                :STD_LOGIC_VECTOR(15 downto 0) := x"8089"; ---internal Register input
  112.         CONSTANT ADDR_INOUT_485EN1        :STD_LOGIC_VECTOR(15 downto 0) := x"808A"; ---internal Register input
  113.         CONSTANT ADDR_INOUT_485EN2        :STD_LOGIC_VECTOR(15 downto 0) := x"808B"; ---internal Register input
  114. --        CONSTANT ADDR_INOUT_Z                :STD_LOGIC_VECTOR(15 downto 0) := x"808C"; ---internal Register input
  115. --        CONSTANT ADDR_INOUT_M                :STD_LOGIC_VECTOR(15 downto 0) := x"808D"; ---internal Register input
  116. --        CONSTANT ADDR_INOUT_N                :STD_LOGIC_VECTOR(15 downto 0) := x"808E"; ---internal Register input
  117.         CONSTANT ADDR_INOUT_1032        :STD_LOGIC_VECTOR(15 downto 0) := x"808F"; ---internal Register input


  118. Begin
  119.        
  120.         Address_p:process(ALE)----AddressLatch
  121.         begin
  122.                 if ALE'event and ALE = '0' and ALE'LAST_VALUE='1' then
  123.                         C51_Addr16 <= P2(5 downto 5)&"00"&P2(4 downto 0)&P0;
  124.                 end if;
  125.         end process;
  126.        
  127.         REG_IN_AUDBY(7 downto 0) <= "1111111" & AUDBY;
  128.         REG_IN_WJA(7 downto 0) <= KEY1(7 downto 0);
  129.         REG_IN_WJB(7 downto 0) <= KEY2(7 downto 0);
  130.         REG_IN_S1(4 downto 0) <= S1(4 downto 0);
  131.         REG_IN_S2(4 downto 0) <= S2(4 downto 0);
  132.         REG_IN_H1(3 downto 0) <= H1(3 downto 0);
  133.         REG_IN_H2(3 downto 0) <= H2(3 downto 0);
  134.         REG_IN_COIN1(1 downto 0) <= COIN1(1 downto 0);
  135.         REG_IN_COIN2(1 downto 0) <= COIN2(1 downto 0);
  136.         REG_IN_MB(3 downto 0) <= MB_C(3 downto 0);
  137.         REG_IN_SW1(7 downto 0) <= SW1(7 downto 0);
  138.         REG_IN_LCDBY1(7 downto 0) <= "1111111" & LCDBY1;
  139.         REG_IN_LCDBY2(7 downto 0) <= "1111111" & LCDBY2;
  140.         REG_IN_485BY1(7 downto 0) <= "1111111" & SP485BY1;
  141.         REG_IN_485BY2(7 downto 0) <= "1111111" & SP485BY2;
  142.        
  143.         WR_EN <= (WR AND RD) OR WR;-----WR Enable
  144.         RD_EN <= (WR AND RD) OR RD;-----RD Enable
  145.        
  146.         -----Read FPGA internal Register-----------
  147.         P0<=REG_IN_AUDBY(7 downto 0) when C51_Addr16 = ADDR_IN_AUDIO and RD_EN='0' else
  148.                 REG_IN_WJA(7 downto 0) when C51_Addr16 = ADDR_IN_WJA and RD_EN='0' else
  149.                 REG_IN_WJB(7 downto 0) when C51_Addr16 = ADDR_IN_WJB and RD_EN='0' else
  150.                 REG_IN_S1(7 downto 0) when C51_Addr16 = ADDR_IN_S1 and RD_EN='0' else
  151.                 REG_IN_S2(7 downto 0) when C51_Addr16 = ADDR_IN_S2 and RD_EN='0' else
  152.                 REG_IN_H1(7 downto 0) when C51_Addr16 = ADDR_IN_H1 and RD_EN='0' else
  153.                 REG_IN_H2(7 downto 0) when C51_Addr16 = ADDR_IN_H2 and RD_EN='0' else
  154.                 REG_IN_COIN1(7 downto 0) when C51_Addr16 = ADDR_IN_COIN1 and RD_EN='0' else
  155.                 REG_IN_COIN2(7 downto 0) when C51_Addr16 = ADDR_IN_COIN2 and RD_EN='0' else
  156.                 REG_IN_MB(7 downto 0) when C51_Addr16 = ADDR_IN_MB and RD_EN='0' else
  157.                 REG_IN_SW1(7 downto 0) when C51_Addr16 = ADDR_IN_SW1 and RD_EN='0' else
  158. --                REG_IN_SW2(7 downto 0) when C51_Addr16 = ADDR_IN_SW2 and RD_EN='0' else
  159.                 REG_IN_LCDBY1(7 downto 0) when C51_Addr16 = ADDR_IN_LCDBY1 and RD_EN='0' else
  160.                 REG_IN_LCDBY2(7 downto 0) when C51_Addr16 = ADDR_IN_LCDBY2 and RD_EN='0' else
  161.                 REG_IN_485BY1(7 downto 0) when C51_Addr16 = ADDR_IN_485BY1 and RD_EN='0' else
  162.                 REG_IN_485BY2(7 downto 0) when C51_Addr16 = ADDR_IN_485BY2 and RD_EN='0' else
  163.                
  164.                 REG_INOUT_LED0(7 downto 0) when C51_Addr16 = ADDR_INOUT_LED0 and RD_EN='0' else
  165.                 REG_INOUT_LEDA(7 downto 0) when C51_Addr16 = ADDR_INOUT_LEDA and RD_EN='0' else
  166.                 REG_INOUT_LEDB(7 downto 0) when C51_Addr16 = ADDR_INOUT_LEDB and RD_EN='0' else
  167.                 REG_INOUT_LED8(7 downto 0) when C51_Addr16 = ADDR_INOUT_LED8 and RD_EN='0' else
  168.                 REG_INOUT_LEDY(7 downto 0) when C51_Addr16 = ADDR_INOUT_LEDY and RD_EN='0' else
  169.                 REG_INOUT_SSR1(7 downto 0) when C51_Addr16 = ADDR_INOUT_SSR1 and RD_EN='0' else
  170.                 REG_INOUT_SSR2(7 downto 0) when C51_Addr16 = ADDR_INOUT_SSR2 and RD_EN='0' else
  171.                 REG_INOUT_SSL1(7 downto 0) when C51_Addr16 = ADDR_INOUT_SSL1 and RD_EN='0' else
  172.                 REG_INOUT_SSL2(7 downto 0) when C51_Addr16 = ADDR_INOUT_SSL2 and RD_EN='0' else
  173.                 REG_INOUT_MB(7 downto 0) when C51_Addr16 = ADDR_INOUT_MB and RD_EN='0' else
  174.                 REG_INOUT_485EN1(7 downto 0) when C51_Addr16 = ADDR_INOUT_485EN1 and RD_EN='0' else
  175.                 REG_INOUT_485EN2(7 downto 0) when C51_Addr16 = ADDR_INOUT_485EN2 and RD_EN='0' else
  176. --                REG_INOUT_Z(7 downto 0) when C51_Addr16 = ADDR_INOUT_Z and RD_EN='0' else
  177. --                REG_INOUT_M(7 downto 0) when C51_Addr16 = ADDR_INOUT_M and RD_EN='0' else
  178. --                REG_INOUT_N(7 downto 0) when C51_Addr16 = ADDR_INOUT_N and RD_EN='0' else
  179.                 REG_INOUT_1032(7 downto 0) when C51_Addr16 = ADDR_INOUT_1032 and RD_EN='0' else
  180.                 "ZZZZZZZZ";

  181.        
  182.         C51_Write_FPGA: process(WR_EN)----Write FPGA interal Register
  183.         begin
  184.                 if WR'EVENT and WR'LAST_VALUE='1' and WR_EN='0' then                
  185.                         case C51_Addr16 is
  186.                                 when ADDR_INOUT_LED0=>REG_INOUT_LED0(7 downto 0)<=P0;
  187.                                 when ADDR_INOUT_LEDA=>REG_INOUT_LEDA(7 downto 0)<=P0;
  188.                                 when ADDR_INOUT_LEDB=>REG_INOUT_LEDB(7 downto 0)<=P0;
  189.                                 when ADDR_INOUT_LED8=>REG_INOUT_LED8(7 downto 0)<=P0;
  190.                                 when ADDR_INOUT_LEDY=>REG_INOUT_LEDY(7 downto 0)<=P0;
  191.                                 when ADDR_INOUT_SSR1=>REG_INOUT_SSR1(7 downto 0)<=P0;
  192.                                 when ADDR_INOUT_SSR2=>REG_INOUT_SSR2(7 downto 0)<=P0;
  193.                                 when ADDR_INOUT_SSL1=>REG_INOUT_SSL1(7 downto 0)<=P0;
  194.                                 when ADDR_INOUT_SSL2=>REG_INOUT_SSL2(7 downto 0)<=P0;
  195.                                 when ADDR_INOUT_MB=>REG_INOUT_MB(7 downto 0)<=P0;
  196.                                 when ADDR_INOUT_485EN1=>REG_INOUT_485EN1(7 downto 0)<=P0;
  197.                                 when ADDR_INOUT_485EN2=>REG_INOUT_485EN2(7 downto 0)<=P0;
  198. --                                when ADDR_INOUT_Z=>REG_INOUT_Z(7 downto 0)<=P0;
  199. --                                when ADDR_INOUT_M=>REG_INOUT_M(7 downto 0)<=P0;
  200. --                                when ADDR_INOUT_N=>REG_INOUT_N(7 downto 0)<=P0;
  201.                                 when ADDR_INOUT_1032=>REG_INOUT_1032(7 downto 0)<=P0;
  202.                                 when OTHERS=>NULL;
  203.                         end case;
  204.                 end if;
  205.         end process;
  206.        
  207.         LED0(0 downto 0) <= REG_INOUT_LED0(0 downto 0);
  208.         LEDA(1 downto 0) <= REG_INOUT_LEDA(1 downto 0);
  209.         LEDB(1 downto 0) <= REG_INOUT_LEDB(1 downto 0);
  210.         LED8(7 downto 0) <= REG_INOUT_LED8(7 downto 0);
  211.         LEDY(3 downto 0) <= REG_INOUT_LEDY(3 downto 0);
  212.         SSR1 <= REG_INOUT_SSR1(0 downto 0);
  213.         SSR2 <= REG_INOUT_SSR2(0 downto 0);
  214.         SSL1 <= REG_INOUT_SSL1(0 downto 0);
  215.         SSL2 <= REG_INOUT_SSL2(0 downto 0);
  216.         MB_O(3 downto 0) <= REG_INOUT_MB(3 downto 0);
  217. --        MZ(1 downto 0) <= REG_INOUT_Z(1 downto 0);
  218. --        MM(1 downto 0) <= REG_INOUT_M(1 downto 0);
  219. --        ST6600(2 downto 0) <= REG_INOUT_N(2 downto 0);
  220.         ST1032(3 downto 0) <= REG_INOUT_1032(3 downto 0);

  221.         SP485EN1_O(0 downto 0) <= REG_INOUT_485EN1(0 downto 0);
  222.         SP485EN2_O(0 downto 0) <= REG_INOUT_485EN2(0 downto 0);
  223.        
  224. END C51_FPGA_BUS;
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一只鸟敢站在脆弱的枝条上歇脚,它依仗的不是枝条不会断,而是自己有翅膀,会飞。

出0入34汤圆

发表于 2018-8-2 11:34:25 | 显示全部楼层
用 51 的 ALE 做一个 EDGE 的输入来控制,简单的说就是放一颗 74373 来做地址解码的处理行不?!

出0入0汤圆

发表于 2018-8-11 20:36:22 | 显示全部楼层
看了下时序图,我总结如下;ALE的下降沿你用来锁存地址,WR的上升沿你读入数据,RD的下降沿你吧给定地址的数据输出
回帖提示: 反政府言论将被立即封锁ID 在按“提交”前,请自问一下:我这样表达会给举报吗,会给自己惹麻烦吗? 另外:尽量不要使用Mark、顶等没有意义的回复。不得大量使用大字体和彩色字。【本论坛不允许直接上传手机拍摄图片,浪费大家下载带宽和论坛服务器空间,请压缩后(图片小于1兆)才上传。压缩方法可以在微信里面发给自己(不要勾选“原图),然后下载,就能得到压缩后的图片】。另外,手机版只能上传图片,要上传附件需要切换到电脑版(不需要使用电脑,手机上切换到电脑版就行,页面底部)。
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