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发表于 2007-12-19 11:44:53
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// Chipcon
// Product = CC2500
// Chip version = E
// Crystal accuracy = 40 ppm
// X-tal frequency = 26 MHz
// RF output power = 0 dBm
// RX filterbandwidth = 540.000000 kHz
// Deviation = 0.000000
// Datarate = 250.000000 kbps
// Modulation = (7) MSK
// Manchester enable = (0) Manchester disabled
// RF Frequency = 2433.000000 MHz
// Channel spacing = 199.950000 kHz
// Channel number = 0
// Optimization = Sensitivity
// Sync mode = (3) 30/32 sync word bits detected
// Format of RX/TX data = (0) Normal mode, use FIFOs for RX and TX
// CRC operation = (1) CRC calculation in TX and CRC check in RX enabled
// Forward Error Correction = (0) FEC disabled
// Length configuration = (1) Variable length packets, packet length configured by the first received byte after sync word.
// Packetlength = 255
// Preamble count = (2) 4 bytes
// Append status = 1
// Address check = (0) No address check
// FIFO autoflush = 0
// Device address = 0
// GDO0 signal selection = ( 6) Asserts when sync word has been sent / received, and de-asserts at the end of the packet
// GDO2 signal selection = (11) Serial Clock
typedef struct
{
uchar fsctrl1; // Frequency synthesizer control.
uchar fsctrl0; // Frequency synthesizer control.
uchar freq2; // Frequency control word, high byte.
uchar freq1; // Frequency control word, middle byte.
uchar freq0; // Frequency control word, low byte.
uchar mdmcfg4; // Modem configuration.
uchar mdmcfg3; // Modem configuration.
uchar mdmcfg2; // Modem configuration.
uchar mdmcfg1; // Modem configuration.
uchar mdmcfg0; // Modem configuration.
uchar channr; // Channel number.
uchar deviatn; // Modem deviation setting (when FSK modulation is enabled).
uchar frend1; // Front end RX configuration.
uchar frend0; // Front end RX configuration.
uchar mcsm0; // Main Radio Control State Machine configuration.
uchar foccfg; // Frequency Offset Compensation Configuration.
uchar bscfg; // Bit synchronization Configuration.
uchar agcctrl2; // AGC control.
uchar agcctrl1; // AGC control.
uchar agcctrl0; // AGC control.
uchar fscal3; // Frequency synthesizer calibration.
uchar fscal2; // Frequency synthesizer calibration.
uchar fscal1; // Frequency synthesizer calibration.
uchar fscal0; // Frequency synthesizer calibration.
uchar fstest; // Frequency synthesizer calibration.
uchar test2; // Various test settings.
uchar test1; // Various test settings.
uchar test0; // Various test settings.
uchar iocfg2; // GDO2 output pin configuration.
uchar iocfg0d; // GDO0 output pin configuration. Refer to SmartRF? Studio User Manual for detailed pseudo register explanation.
uchar pktctrl1; // Packet automation control.
uchar pktctrl0; // Packet automation control.
uchar addr; // Device address.
uchar pktlen; // Packet length.
} RF_SETTING;
const RF_SETTING rfSetting PROGMEM =
{
0x07, // FSCTRL1 Frequency synthesizer control.
0x00, // FSCTRL0 Frequency synthesizer control.
0x5D, // FREQ2 Frequency control word, high byte.
0x93, // FREQ1 Frequency control word, middle byte.
0xB1, // FREQ0 Frequency control word, low byte.
0x2D, // MDMCFG4 Modem configuration.
0x3B, // MDMCFG3 Modem configuration.
0x73, // MDMCFG2 Modem configuration.
0x22, // MDMCFG1 Modem configuration.
0xF8, // MDMCFG0 Modem configuration.
0x00, // CHANNR Channel number.
0x00, // DEVIATN Modem deviation setting (when FSK modulation is enabled).
0xB6, // FREND1 Front end RX configuration.
0x10, // FREND0 Front end RX configuration.
0x18, // MCSM0 Main Radio Control State Machine configuration.
0x1D, // FOCCFG Frequency Offset Compensation Configuration.
0x1C, // BSCFG Bit synchronization Configuration.
0xC7, // AGCCTRL2 AGC control.
0x00, // AGCCTRL1 AGC control.
0xB2, // AGCCTRL0 AGC control.
0xEA, // FSCAL3 Frequency synthesizer calibration.
0x0A, // FSCAL2 Frequency synthesizer calibration.
0x00, // FSCAL1 Frequency synthesizer calibration.
0x11, // FSCAL0 Frequency synthesizer calibration.
0x59, // FSTEST Frequency synthesizer calibration.
0x88, // TEST2 Various test settings.
0x31, // TEST1 Various test settings.
0x0B, // TEST0 Various test settings.
0x0B, // IOCFG2 GDO2 output pin configuration.
0x06, // IOCFG0D GDO0 output pin configuration. Refer to SmartRF?Studio User Manual for detailed pseudo register explanation.
0x04, // PKTCTRL1 Packet automation control.
0x05, // PKTCTRL0 Packet automation control.
0x00, // ADDR Device address.
0x15 // PKTLEN Packet length.
};
/*
---------------------------------------------------------------------
Function : SpiTxRxuchar()
Description : 发送同时接收数据字节(采用SPI模块的查询方式)
---------------------------------------------------------------------
*/
uchar SpiTxRxuchar(uchar dat)
{
uchar volatile temp;
SPDR = dat; // 启动数据传输
while(!(SPSR & (1 << SPIF)))
{
//asm("wdr");
} // 等待传输结束
temp = SPDR;
return (temp);
}
/*
---------------------------------------------------------------------
Function : ResetCCxx00()
Description : 复位CC2500
---------------------------------------------------------------------
* min 40 us
* <------------------>
* CSn |--| |--------------------| |-----
* | | | | |
* -- ------------
*
* MISO |----|
* -----------------------------| | |
* -- ---------
* Unknown / don't care
* SRES done
---------------------------------------------------------------------
*/
void ResetCCxx00(void)
{
CSn_EN(); // 片选
while (GDO1_IN()) //
{
//asm("wdr");
}
SpiTxRxuchar(SRES); //写入复位命令
/*while (GDO1_IN()) //
{
//asm("wdr");
}*/
CSn_DIS(); // 取消片选
}
/*
---------------------------------------------------------------------
Function : PowerUpResetCCxx00()
Description : 上电复位
---------------------------------------------------------------------
*/
void PowerUpResetCCxx00(void)
{
CSn_DIS();
_delay_ms(1);
CSn_EN();
_delay_ms(1);
CSn_DIS();
_delay_ms(41);
ResetCCxx00();
}
/*
---------------------------------------------------------------------
Function : halSpiWriteReg()
Description : 单字节配置
---------------------------------------------------------------------
*/
void halSpiWriteReg(uchar addr, uchar value)
{
CSn_EN(); // 片选
while(GDO1_IN())
{
//asm("wdr");
}
SpiTxRxuchar(addr); // 写地址
SpiTxRxuchar(value);// 写入配置
CSn_DIS(); // 取消片选
}
/*
---------------------------------------------------------------------
Function : halSpiWriteBurstReg()
Description : n字节连续配置
---------------------------------------------------------------------
*/
void halSpiWriteBurstReg(uchar addr, uchar * pbuf, uchar n)
{
uchar i;
CSn_EN(); // 片选
while(GDO1_IN())
{
//asm("wdr");
}
SpiTxRxuchar(addr | WRITE_BURST);
for (i=0; i<n; i++)
{
SpiTxRxuchar(pbuf); // 传送数据
}
CSn_DIS(); // 取消片选
}
/*
---------------------------------------------------------------------
Function : halSpiStrobe()
Description : 纯命令
---------------------------------------------------------------------
*/
void halSpiStrobe(uchar strobe)
{
CSn_EN(); // 片选
while(GDO1_IN()) //
{
//asm("wdr");
}
SpiTxRxuchar(strobe);
CSn_DIS(); // 取消片选
}
/*
---------------------------------------------------------------------
Function : halSpiReadReg()
Description : 单寄存器(字节)读取
---------------------------------------------------------------------
*/
uchar halSpiReadReg(uchar addr)
{
uchar volatile rdat;
CSn_EN(); // 片选
while (GDO1_IN())
{
//asm("wdr");
}
SpiTxRxuchar(addr | READ_SINGLE);//读寄存器命令
SpiTxRxuchar(0);
CSn_DIS(); // 取消片选
return (rdat);
}
/*
---------------------------------------------------------------------
Function : halSpiReadBurstReg()
Description : n个寄存器(字节)读取
---------------------------------------------------------------------
*/
void halSpiReadBurstReg(uchar addr, uchar *pbuf, uchar n)
{
uchar i;
CSn_EN(); // 片选
while (GDO1_IN())
{
//asm("wdr");
}
SpiTxRxuchar(addr | READ_BURST);
for (i = 0; i < n; i++)
{
pbuf = SpiTxRxuchar(0);
}
CSn_DIS(); // 取消片选
}
/*
---------------------------------------------------------------------
Function : halSpiReadStatus()
Description : 读取的状态
---------------------------------------------------------------------
*/
uchar halSpiReadStatus(uchar addr)
{
uchar volatile rdat;
CSn_EN(); // 片选
while (GDO1_IN())
{
//asm("wdr");
}
SpiTxRxuchar(addr | READ_BURST); //写入要读的状态寄存器的地址同时写入读命令
rdat = SpiTxRxuchar(0);
CSn_DIS(); // 取消片选
return (rdat);
}
/*
---------------------------------------------------------------------
Function : CC2500Init()
Description : 配置CC2500的寄存器
---------------------------------------------------------------------
*/
void CC2500Init(void)
{
halSpiWriteReg(FSCTRL1, rfSetting.fsctrl1); // Frequency synthesizer control.
halSpiWriteReg(FSCTRL0, rfSetting.fsctrl0); // Frequency synthesizer control.
halSpiWriteReg(FREQ2, rfSetting.freq2); // Frequency control word, high byte.
halSpiWriteReg(FREQ1, rfSetting.freq1); // Frequency control word, middle byte.
halSpiWriteReg(FREQ0, rfSetting.freq0); // Frequency control word, low byte.
halSpiWriteReg(MDMCFG4, rfSetting.mdmcfg4); // Modem configuration.
halSpiWriteReg(MDMCFG3, rfSetting.mdmcfg3); // Modem configuration.
halSpiWriteReg(MDMCFG2, rfSetting.mdmcfg2); // Modem configuration.
halSpiWriteReg(MDMCFG1, rfSetting.mdmcfg1); // Modem configuration.
halSpiWriteReg(MDMCFG0, rfSetting.mdmcfg0); // Modem configuration.
halSpiWriteReg(CHANNR, rfSetting.channr); // Channel number.
halSpiWriteReg(DEVIATN, rfSetting.deviatn); // Modem deviation setting (when FSK modulation is enabled).
halSpiWriteReg(FREND1, rfSetting.frend1); // Front end RX configuration.
halSpiWriteReg(FREND0, rfSetting.frend0); // Front end RX configuration.
halSpiWriteReg(MCSM0, rfSetting.mcsm0); // Main Radio Control State Machine configuration.
halSpiWriteReg(FOCCFG, rfSetting.foccfg); // Frequency Offset Compensation Configuration.
halSpiWriteReg(BSCFG, rfSetting.bscfg); // Bit synchronization Configuration.
halSpiWriteReg(AGCCTRL2, rfSetting.agcctrl2); // AGC control.
halSpiWriteReg(AGCCTRL1, rfSetting.agcctrl1); // AGC control.
halSpiWriteReg(AGCCTRL0, rfSetting.agcctrl0); // AGC control.
halSpiWriteReg(FSCAL3, rfSetting.fscal3); // Frequency synthesizer calibration.
halSpiWriteReg(FSCAL2, rfSetting.fscal2); // Frequency synthesizer calibration.
halSpiWriteReg(FSCAL1, rfSetting.fscal1); // Frequency synthesizer calibration.
halSpiWriteReg(FSCAL0, rfSetting.fscal0); // Frequency synthesizer calibration.
halSpiWriteReg(FSTEST, rfSetting.fstest); // Frequency synthesizer calibration.
halSpiWriteReg(TEST2, rfSetting.test2); // Various test settings.
halSpiWriteReg(TEST1, rfSetting.test1); // Various test settings.
halSpiWriteReg(TEST0, rfSetting.test0); // Various test settings.
halSpiWriteReg(IOCFG2, rfSetting.iocfg2); // GDO2 output pin configuration.
halSpiWriteReg(IOCFG0D, rfSetting.iocfg0d); // GDO0 output pin configuration. Refer to SmartRF? Studio User Manual for detailed pseudo register explanation.
halSpiWriteReg(PKTCTRL1, rfSetting.pktctrl1); // Packet automation control.
halSpiWriteReg(PKTCTRL0, rfSetting.pktctrl0); // Packet automation control.
halSpiWriteReg(ADDR, rfSetting.addr); // Device address.
halSpiWriteReg(PKTLEN, rfSetting.pktlen); // Packet length.
}
/*
---------------------------------------------------------------------
Function : SendPacket()
Description : 发送主叫数据
---------------------------------------------------------------------
DESCRIPTION :
This function can be used to transmit a packet with packet length
up to 63 bytes. To use this function, GD00 must be configured to be
asserted when sync word is sent and de-asserted at the end of the
packet => halSpiWriteReg(IOCFG0, 0x06);The function implements polling
of GDO0. First it waits for GD00 to be set and then it waits for it to
be cleared.
---------------------------------------------------------------------
ARGUMENTS :
uchar *pbuf
Pointer to a buffer containing the data that are going to be transmitted
uchar n
The size of the txBuffer
---------------------------------------------------------------------
*/
void halRfSendPacket(uchar *pbuf, uchar n)
{
halSpiWriteBurstReg(TXFIFO, pbuf, n);
halSpiStrobe(STX);
while (!GDO0_IN()) // Wait for GDO0 to be set -> sync transmitted
{
//asm("wdr");
}
while (GDO0_IN()) // Wait for GDO0 to be cleared -> end of packet
{
//asm("wdr");
}
}
/*
---------------------------------------------------------------------
Function : halRfRecivePacket()
Description : 使用接收数据
---------------------------------------------------------------------
DESCRIPTION :
This function can be used to receive a packet of variable packet
length (first byte in the packet must be the length byte). The packet
length should not exceed the RX FIFO size. To use this function, GD00
must be configured to be asserted when sync word is sent and de-asserted
at the end of the packet => halSpiWriteReg(IOCFG0, 0x06); Also,
APPEND_STATUS in the PKTCTRL1 register must be enabled. The function
implements polling of GDO0. First it waits for GD00 to be set and then
it waits for it to be cleared. After the GDO0 pin has been de-asserted,
the RXBYTES register is read to make sure that there are bytes in the
FIFO. This is because the GDO signal will indicate sync received even
if the FIFO is flushed due to address filtering, CRC filtering, or
packet length filtering.
---------------------------------------------------------------------
ARGUMENTS :
uchar *pbuf
Pointer to the buffer where the incoming data should be stored
uchar *len
Pointer to a variable containing the size of the buffer where
the incoming data should be stored. After this function returns, that
variable holds the packet length.
RETURN VALUE:
uchar
TRUE: CRC OK
FALSE: CRC NOT OK (or no packet was put in the RX FIFO due to filtering)
---------------------------------------------------------------------
*/
uchar halRfRecivePacket(uchar *pbuf, uchar *len)
{
uchar status[2];
uchar pktlen;
halSpiStrobe(SRX);
while (!GDO0_IN())
{
//asm("wdr");
} // Wait for GDO0 to be set -> sync received
while (GDO0_IN())
{
//asm("wdr");
} // Wait for GDO0 to be cleared -> end of packet
if ((halSpiReadStatus(RXBYTES) & BYTES_IN_RXFIFO))
{
pktlen = halSpiReadReg(RXFIFO); // Read length byte
if (pktlen <= *len) // Read data from RX FIFO and store in rxBuffer
{
halSpiReadBurstReg(RXFIFO, pbuf, pktlen);
*len = pktlen;
halSpiReadBurstReg(RXFIFO, status, 2); // Read the 2 appended status bytes (status[0] = RSSI, status[1] = LQI)
return (status[0] & CRC_OK); // MSB of LQI is the CRC_OK bit
return TRUE;
}
else
{
*len = pktlen;
halSpiStrobe(SFRX); // Flush RX FIFO
return FALSE;
}
}
else
{
return FALSE;
}
} |
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