发一个网络上找不到的资源，spiflash控制器的verilog代码，前两天自己做的，板上验证通过 (amobbs.com 阿莫电子技术论坛) -

beichengjun 发表于 2011-3-1 13:30:13

发一个网络上找不到的资源，spiflash控制器的verilog代码，前两天自己做的，板上验证通过

module spiflashIV(
data_ok,
clk,
addr,
mode,// 1 is write,0 is read
txdata,
rxdata,
ld_addr,//start onecommand
cs,
sck,
miso_temp,
mosi,
NUM
);

input addr;
inputclk;
inputmode;
inputtxdata;
inputld_addr;//start one bye translate
input wire miso_temp;
input NUM;

output cs;
output sck;
output mosi;
outputrxdata;
output data_ok;

reg reset_count;
reg reset;
always@(posedge clk)
begin
reset_count<=reset_count;
if(reset_count<8'h01)begin
reset_count<=reset_count+1'b1;
reset<=1'b0;
end
else begin
reset<=1'b1;
end
end

wire miso;

assign miso=miso_temp;
reg cs;
reg data_ok;
reg state;
reg rxdata;
reg rxdata_temp;
regSTATE;

regnum;
always@(posedge clk or negedge reset)begin
if(!reset)begin
cs<=1'b1;
state<=7'b0000000;
data_ok<=1'b0;
rxdata<=8'b00000000;
STATE<=2'b00;
num<=10'd0;
end
else begin
cs<=cs;
state<=state;
data_ok<=data_ok;
rxdata<=rxdata;
STATE<=STATE;
num<=num;
if(ld_addr)begin
cs<=1'b0;
STATE<=2'b01;
end

case(STATE)
2'b01:
begin
if(state<7'd64)begin
state<=state+1'b1;
end
else begin
STATE<=2'd2;
state<=7'd0;
end
end
2'b10:
begin
if(num<NUM)begin
if(state<7'd16)begin
state<=state+1'b1;
end
else if(state<=7'd16)begin
state<=7'd17;
data_ok<=1'b1;
rxdata<=rxdata_temp;
end
else begin
state<=7'd0;
data_ok<=1'b0;
num<=num+1'b1;
end
end
else begin
cs<=1'b1;
STATE<=2'b00;
num<=10'd0;
end
end
default:begin end
endcase

end
end

reg mosi;
reg sck;
always@(negedge clk or negedge reset)begin
if(!reset)begin
sck<=1'b0;
mosi<=1'b0;
rxdata_temp<=8'b00000000;
end
else begin
sck<=sck;
mosi<=mosi;
rxdata_temp<=rxdata_temp;
case(STATE)
2'b01:
case(state)
7'd1:begin sck<=1'b1; end
7'd2:begin sck<=1'b0; mosi<=1'b0; end
      7'd3:begin sck<=1'b1; end
7'd4:begin sck<=1'b0; mosi<=1'b0; end
7'd5:begin sck<=1'b1; end
7'd6:begin sck<=1'b0; mosi<=1'b0;end
7'd7:begin sck<=1'b1; end
7'd8:begin sck<=1'b0; mosi<=1'b0;end
      7'd9:begin sck<=1'b1;end
7'd10:begin sck<=1'b0; mosi<=1'b0;end
7'd11:begin sck<=1'b1; end
7'd12:begin sck<=1'b0; mosi<=1'b1;end
7'd13:begin sck<=1'b1; end
7'd14:begin sck<=1'b0; mosi<=1'b1;end
7'd15:begin sck<=1'b1; end
7'd16:begin sck<=1'b0; mosi<=addr;end

7'd17:begin sck<=1'b1; end
7'd18:begin sck<=1'b0; mosi<=addr;end
      7'd19:begin sck<=1'b1; end
7'd20:begin sck<=1'b0; mosi<=addr;end
7'd21:begin sck<=1'b1;end
7'd22:begin sck<=1'b0; mosi<=addr;end
7'd23:begin sck<=1'b1;end
7'd24:begin sck<=1'b0; mosi<=addr; end
      7'd25:begin sck<=1'b1; end
7'd26:begin sck<=1'b0;mosi<=addr;end
7'd27:begin sck<=1'b1; end
7'd28:begin sck<=1'b0; mosi<=addr;end
7'd29:begin sck<=1'b1; end
7'd30:begin sck<=1'b0; mosi<=addr;end
7'd31:begin sck<=1'b1; end
7'd32:begin sck<=1'b0; mosi<=addr;end

7'd33:begin sck<=1'b1;end
7'd34:begin sck<=1'b0; mosi<=addr;end
      7'd35:begin sck<=1'b1;end
7'd36:begin sck<=1'b0; mosi<=addr;end
7'd37:begin sck<=1'b1;end
7'd38:begin sck<=1'b0;mosi<=addr;end
7'd39:begin sck<=1'b1; end
7'd40:begin sck<=1'b0; mosi<=addr;end
      7'd41:begin sck<=1'b1;end
7'd42:begin sck<=1'b0; mosi<=addr; end
7'd43:begin sck<=1'b1; end
7'd44:begin sck<=1'b0; mosi<=addr;end
7'd45:begin sck<=1'b1;end
7'd46:begin sck<=1'b0; mosi<=addr;end
7'd47:begin sck<=1'b1;end
7'd48:begin sck<=1'b0; mosi<=addr;end

7'd49:begin sck<=1'b1;end
7'd50:begin sck<=1'b0; mosi<=addr;end
      7'd51:begin sck<=1'b1;end
7'd52:begin sck<=1'b0; mosi<=addr;end
7'd53:begin sck<=1'b1;end
7'd54:begin sck<=1'b0; mosi<=addr;end
7'd55:begin sck<=1'b1;end
7'd56:begin sck<=1'b0; mosi<=addr;end
      7'd57:begin sck<=1'b1;end
7'd58:begin sck<=1'b0; mosi<=addr;end
7'd59:begin sck<=1'b1;end
7'd60:begin sck<=1'b0; mosi<=addr;end
7'd61:begin sck<=1'b1;end
7'd62:begin sck<=1'b0; mosi<=addr;end
7'd63:begin sck<=1'b1; end
7'd64:begin sck<=1'b0; mosi<=1'b0;end
default:begin end
endcase
2'b10:
case(state)
7'd1:begin sck<=1'b1; rxdata_temp<=miso;end
7'd2:begin sck<=1'b0; mosi<=1'b0; end
      7'd3:begin sck<=1'b1; rxdata_temp<=miso;end
7'd4:begin sck<=1'b0; mosi<=1'b0; end
7'd5:begin sck<=1'b1; rxdata_temp<=miso;end
7'd6:begin sck<=1'b0; mosi<=1'b0; end
7'd7:begin sck<=1'b1; rxdata_temp<=miso;end
7'd8:begin sck<=1'b0; mosi<=1'b0; end
      7'd9:begin sck<=1'b1; rxdata_temp<=miso;end
7'd10:begin sck<=1'b0; mosi<=1'b0; end
7'd11:begin sck<=1'b1; rxdata_temp<=miso;end
7'd12:begin sck<=1'b0; mosi<=1'b0;end
7'd13:begin sck<=1'b1; rxdata_temp<=miso; end
7'd14:begin sck<=1'b0; mosi<=1'b0;end
7'd15:begin sck<=1'b1; rxdata_temp<=miso;end
7'd16:begin sck<=1'b0; mosi<=1'b0;end
default:begin end
endcase
default:begin end
endcase
end
end
endmodule

http://cache.amobbs.com/bbs_upload782111/files_36/ourdev_619156AFXQFF.JPG
(原文件名:lattice内嵌逻辑分析仪_spiflash读时序.JPG)

wso75839840 发表于 2011-3-1 16:59:32

mark

HYFAVR 发表于 2011-3-1 18:03:57

mark

wajlh 发表于 2011-3-1 18:25:48

make

kneken 发表于 2011-3-1 18:45:26

mark

bobqq 发表于 2011-3-1 18:57:36

mark

kunpeng032 发表于 2011-3-1 20:53:39

mark

guolh 发表于 2011-3-2 08:06:13

支持，要是加点说明就更好了！

wxx116zh 发表于 2011-3-2 08:20:48

mark

hoho34 发表于 2011-3-2 08:27:51

mark

nightmara 发表于 2011-3-2 09:49:55

mark

liquanmin 发表于 2011-3-3 16:54:39

回复【10楼】nightmara
-----------------------------------------------------------------------

楼主：你所用芯片的型号是什么啊？

liquanmin 发表于 2011-3-3 16:54:42

回复【10楼】nightmara
-----------------------------------------------------------------------

楼主：你所用芯片的型号是什么啊？

hnoys 发表于 2012-2-10 15:49:50

mark!

janno0258 发表于 2012-6-18 19:41:48

markddddd

jlhgold 发表于 2012-6-18 20:34:39

这不会是专门用来串口烧写flash的吧？

moxiaoxiong 发表于 2012-6-18 23:10:47

mark lz

alta 发表于 2012-12-24 14:15:29

mark

yao2013lin 发表于 2014-5-14 09:31:58

mark{:handshake:}

xgbing88 发表于 2014-5-14 12:37:19

mark，顶一下

andmain999 发表于 2014-6-1 08:48:11

感谢分享{:victory:}

dzf050727 发表于 2014-9-11 11:25:29

收藏，买的板子在路上，到了后一定用楼主的代码试下。谢谢分享！

mcupro 发表于 2014-10-21 00:29:08

收了，这操作方式简洁高效，是好的例子

lanting1025 发表于 2014-10-21 20:21:44

mark，赞

qiushui_007 发表于 2014-10-21 20:28:28

网上找不到, LZ自己实现. 赞一个

flyfox8 发表于 2014-10-25 09:51:16

搞下来看看，话说楼主用的是哪款flash芯片。

cnxh 发表于 2014-10-25 10:34:09

谢谢,收藏下

lyyszhang 发表于 2014-11-3 15:06:32

给点注释就好看了

kejinkun 发表于 2014-11-6 20:46:30

太好了，正需要呢，谢谢了

fdcnuaa 发表于 2016-6-12 16:42:01

mark 一下

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发一个网络上找不到的资源，spiflash控制器的verilog代码，前两天自己做的，板上验证通过