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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------四倍频模块---------------
entity pulse is
port(
CLK: in std_logic ; --输入时钟
RST_N: in std_logic ; --复位，低有效
AA: in std_logic ; --A输入
BB: in std_logic ; --B输入
DIR: out std_logic ; --方向信号输出
PUL: out std_logic ); --倍频后时钟输出
end;
architecture bhv of pulse is
type state is (s0,s1,s2,s3,s4);
signal dir_state : state; --方向信号状态
signal pul_state : state; --倍频时钟状态
signal RST : std_logic; --复位信号，高有效
signal dir_buf : std_logic; --方向信号buffer
signal a_buf : std_logic; --A信号buffer
signal b_buf : std_logic; --B信号buffer
signal a_tmp : std_logic;
signal b_tmp : std_logic;
signal pul_buf : std_logic;
signal count : integer range 0 to 64;
signal A : std_logic;
signal B : std_logic;
begin
RST <= not RST_N;
A<=AA;
B<=BB;
-------输入信号同步--------------
process(CLK,RST)
begin
if RST = '1' then
a_buf <= '0';
b_buf <= '0';
elsif CLK'event and CLK = '1' then
a_buf <= a_tmp;
b_buf <= b_tmp;
end if;
end process;
process(CLK,RST)
begin
if RST = '1' then
a_tmp <= '0';
b_tmp <= '0';
elsif CLK'event and CLK = '1' then
a_tmp <= A;
b_tmp <= B;
end if;
end process;
---------产生方向信号-------
process(CLK,RST)
begin
if RST = '1' then
dir_buf <= '0';
dir_state <= s0;
elsif CLK = '1' and CLK'event then
case dir_state is
when s0 =>
if a_buf = '0' then
dir_state <= s1;
else
dir_state <= s2;
end if;
when s1 =>
if a_buf = '1' then
dir_state <= s3;
end if;
when s2 =>
if a_buf = '0' then
dir_state <= s4;
end if;
when s3 =>
if b_buf = '0' then
dir_buf <= '1';
else
dir_buf <= '0';
end if;
dir_state <= s0;
when s4 =>
if b_buf = '1' then
dir_buf <= '1';
else
dir_buf <= '0';
end if;
dir_state <= s0;
when others =>
dir_state <= s0;
end case;
end if;
end process;
-----------产生四倍频时钟-------------
process(RST,CLK)
begin
if RST = '1' then
pul_buf <= '0';
pul_state <= s0;
elsif CLK = '1' and CLK'event then
case pul_state is
when s0 =>
pul_buf <= '0';
if a_buf = b_buf then
pul_state <= s1;
else
pul_state <= s2;
end if;
when s1 =>
if a_buf /= b_buf then
pul_buf <= '1';
pul_state <= s3;
end if;
when s2 =>
if a_buf = b_buf then
pul_buf <= '1';
pul_state <= s3;
end if;
when s3 =>
count <= count + 1;
if count = 63 then
count <= 0;
pul_state <= s0;
end if;
when others =>
pul_state <= s0;
end case;
end if;
end process;
DIR <= dir_buf;
PUL <= pul_buf;
end bhv; |
阿莫论坛20周年了！感谢大家的支持与爱护！！
一只鸟敢站在脆弱的枝条上歇脚，它依仗的不是枝条不会断，而是自己有翅膀，会飞。
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发表于 2010-2-23 13:43:37
楼主
