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最近看到一份代码(VHDL)如下: (由于本人学的是Verilog,以下代码未完全明白)
architecture Behavioral of ALLOW_ZERO_UDP_CHECKSUM is
signal input_reg : std_logic;
begin
line 01: process(clk)
line 02: begin
line 03: if clk'event and clk='1' then
line 04: input_reg<=input;
line 05: end if;
line 06:end process;
line 07:
line 08:process(clk)
line 09:begin
line 10: if clk'event and clk='1' then
line 11: output_to_datasel<=input_reg;
line 12: end if;
line 13:end process;
end Behavioral;
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
问题1 : line 01 段 与 lin 08段等效与如下那段?
A.
always @(posedge clk)
begin
input_reg<=input;
output_to_readen<=input_reg;
end
B.
always @(posedge clk)
begin
input_reg = input;
output_to_readen = input_reg;
end
C:
always @(posedge clk)
begin
input_reg = input;
end
always &(posedge clk)
begin
output_to_readen = input_reg;
end
D:
always @(posedge clk)
begin
input_reg <= input;
end
always &(posedge clk)
begin
output_to_readen <= input_reg;
end
问题二: line 01 段 与 lin 08段 是否与如下代码等效
line 01: process(clk)
line 02: begin
line 03: if clk'event and clk='1' then
line 04: input_reg<=input; //注: 此两条语句均在if有效内(不知道是否需要用begin end)
output_to_datasel<=input_reg;
line 05: end if;
line 06:end process
问题三: VHDL中是否 有 阻塞 与 非阻塞的 说法? 有,又是如何描述的? |
阿莫论坛20周年了！感谢大家的支持与爱护！！
曾经有一段真挚的爱情摆在我的面前，我没有珍惜，现在想起来，还好我没有珍惜……
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发表于 2010-3-4 22:44:04
楼主