这个程序怎么看大家帮忙看看啊

rongtianye · 发表于 2010-6-14 17:31:16

这段程序看不太懂啊看了好久  自己也注释了一些就是形不成概念
谁能帮我注释注释啊

- ================================================================================
-- File: CPimag.vhd
-- Author: olivercamel
-- Date: 4.19.2010

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

-- ================================================================================

entity CPimag is
port
(
-- 定义时钟
clk: in std_logic;
-- 时钟类型
aclr: in std_logic;
-- 输入输出信号说明
inputData: in std_logic_vector (9 downto 0);
outputData: out std_logic_vector (9 downto 0);
-- 简单接口定义
sink_val: in std_logic;
sink_sop: in std_logic;
sink_eop: in std_logic;
source_val: out std_logic;
source_sop: out std_logic;
source_eop: out std_logic;
source_ena: in std_logic
);
end CPimag;

-- ================================================================================

architecture structure of CPimag is

-- --------------------------------------------------------------------------------

-- 库文件描述
component ram_CPimag
PORT
(
aclr : IN STD_LOGIC  := '0';
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
rden : IN STD_LOGIC  := '1';
wraddress : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
wren : IN STD_LOGIC  := '1';
q : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
);
end component;
signal outputRAM: std_logic_vector (9 downto 0);
signal readEna: std_logic;
signal readAdd: std_logic_vector (5 downto 0);
signal readAddInt: integer range 0 to 63;
signal readCount: integer range 0 to 79;
signal writeAdd: std_logic_vector (5 downto 0);
signal writeAddInt: integer range 0 to 63;

-- 信号描述

-- 同步输入信号（使用下降沿触发）
signal inputData_f: std_logic_vector (9 downto 0);
signal sink_val_f: std_logic;
signal sink_sop_f: std_logic;
signal sink_eop_f: std_logic;

-- 开始读信号标志
signal isRead: std_logic;

-- 保护间隔信号
signal interval_source_sop: std_logic;
signal interval_source_eop: std_logic;

-- 延迟信号说明
signal interval_source_val_d1: std_logic;
signal interval_source_val_d2: std_logic;
signal interval_source_sop_d1: std_logic;
signal interval_source_sop_d2: std_logic;
signal interval_source_eop_d1: std_logic;
signal interval_source_eop_d2: std_logic;
signal interval_source_eop_d3: std_logic;

-- --------------------------------------------------------------------------------

begin

-- --------------------------------------------------------------------------------

-- 同步输入信号（采用下降沿）
process(clk,inputData,sink_val,sink_sop,sink_eop)
begin
if falling_edge(clk) then
inputData_f <= inputData;
sink_val_f <= sink_val;
sink_sop_f <= sink_sop;
sink_eop_f <= sink_eop;
end if;
end process;

-- RAM connetion
-- 将输入数据直接存入RAM
u1: ram_CPimag port map
(
clock => clk, aclr => aclr,
data => inputData_f, q => outputRAM,
rden => readEna, rdaddress => readAdd,
wren => sink_val_f, wraddress => writeAdd
);

-- 将整数转变为标准逻辑矢量
readAdd <= conv_std_logic_vector(readAddInt,6);
writeAdd <= conv_std_logic_vector(writeAddInt,6);

--地址生成
process(aclr,clk,sink_val_f,sink_sop_f,sink_eop_f)
begin
if aclr = '1' then
writeAddInt <= 0;
else
if rising_edge(clk) then
if sink_val_f = '1' or sink_sop_f = '1' then
if writeAddInt = 63 then
writeAddInt <= 0;
else
writeAddInt <= writeAddInt + 1;
end if;
elsif sink_eop_f = '1' then
writeAddInt <= 0;
else
writeAddInt <= 0;
end if;
end if;
end if;
end process;

-- flag signal controlling
process(clk,sink_eop_f,interval_source_eop)
begin
if rising_edge(clk) then
if sink_eop_f = '1' then
isRead <= '1';
elsif interval_source_eop = '1' then
isRead <= '0';
end if;
end if;
end process;

-- RAM read enable
process(clk,isRead,source_ena)
begin
if rising_edge(clk) then
if isRead = '1' then
readEna <= source_ena;
else
readEna <= '0';
end if;
end if;
end process;

-- read Count numbers that working when read enable = '1'
process(aclr,clk,readEna)
begin
if aclr = '1' then
readCount <= 0;
else
if rising_edge(clk) then
if readEna = '1' then
if readCount = 79 then
readCount <= 0;
else
readCount <= readCount + 1;
end if;
end if;
end if;
end if;
end process;

-- change readCount into read address
process(readCount)
begin
if readCount <= 15 then
readAddInt <= readCount + 48;
else
readAddInt <= readCount - 16;
end if;
end process;

-- generate source sop eop
process(readEna,readCount)
begin
if readEna = '1' then
if readCount = 78 then -- assert eop before Count = 79
interval_source_sop <= '0';
interval_source_eop <= '1';
elsif readCount = 0 then
interval_source_sop <= '1';
interval_source_eop <= '0';
else
interval_source_sop <= '0';
interval_source_eop <= '0';
end if;
else
interval_source_sop <= '0';
interval_source_eop <= '0';
end if;
end process;

-- delay output interface signals
process(clk,readEna,interval_source_sop,interval_source_eop)
begin
if rising_edge(clk) then
interval_source_val_d1 <= readEna;
interval_source_val_d2 <= interval_source_val_d1;
interval_source_sop_d1 <= interval_source_sop;
interval_source_sop_d2 <= interval_source_sop_d1;
interval_source_eop_d1 <= interval_source_eop;
interval_source_eop_d2 <= interval_source_eop_d1;
interval_source_eop_d3 <= interval_source_eop_d2;
end if;
end process;

-- synchronize output signals using falling edge
process(clk,outputRAM,interval_source_val_d2,
interval_source_sop_d2,interval_source_eop_d3)
begin
if falling_edge(clk) then
outputData <= outputRAM;
source_val <= interval_source_val_d2;
source_sop <= interval_source_sop_d2;
source_eop <= interval_source_eop_d3;
end if;
end process;

-- --------------------------------------------------------------------------------

end structure;

-- ================================================================================

这个程序 怎么看 大家帮忙看看啊

阿莫论坛20周年了！感谢大家的支持与爱护！！

这个程序怎么看大家帮忙看看啊