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我现在在尝试用verilog编写数字存储示波器。遇到一个问题。就是在写触发功能时，我加了一个trigger_begin的上升沿来判断trigger_en信号的有无。但是我存储了512个点后，无法将trigger_en复位。请问怎么解决这个问题。我的代码如下：
module DSO_Version2(clk,out_da2,out_da1,clk_da1,clk_da2,clk_ad,ad_in,out_switch);
input clk;
input [7:0] ad_in;
output [11:0] out_da2,out_da1;
output[7:0] out_switch;
output clk_da1,clk_da2,clk_ad;
reg clk_ad,clk_da1,clk_da2;
reg[11:0] out_da2,out_da1;
reg[11:0] ad_counter;
reg[7:0] clk_counter;
reg[7:0] ad_temp;
reg[7:0] ad_data[511:0];
reg trigger_en,triggerjudge_en;
reg trigger_begin;
wire[7:0] out_switch;
reg[2:0] state,nstate;
parameter idle = 3'b000,
triggerjudge = 3'b001,
AD_RAM = 3'b010,
dis = 3'b011;
always @(posedge clk_ad)
begin
case(state)
idle:
begin
ADSample;
if(trigger_en)
nstate <= AD_RAM;
triggerjudge_en <= 0;
else
nstate <= triggerjudge;
triggerjudge_en <= 1;
end
triggerjudge:
begin
trigger_judge(ad_temp);
nstate <= idle;
end
AD_RAM:
begin
write_RAM(ad_temp);
nstate <= dis;
end
dis:
begin
display(ad_data[ad_counter]);
ad_counter <= ad_counter + 1;
if(ad_counter >= 511)
begin
ad_counter <= 0;
triggerjudge_en <= 1;
nstate <= idle;
end
else
begin
nstate <= idle;
end
end
default:
nstate <= triggerjudge;
endcase
state <= nstate;
end
task ADSample;
if(clk_ad)
ad_temp <= ad_in ^ 8'b1000_0000 ;
endtask
task trigger_judge;
input[7:0] ad_temp;
parameter trigger_level = 100;
if(triggerjudge_en)
begin
if(ad_temp > trigger_level)
trigger_begin <= 1;
else
trigger_begin <= 0;
end
endtask
task write_RAM;
input[7:0] ram_temp;
if(trigger_en)
ad_data[ad_counter] = ram_temp;
endtask
task display;
input[7:0] data;
if(trigger_en)
begin
out_da2[11:4] <= data;
out_da1 <= out_da1 + 8;
end
else
begin
out_da2 <= 0;
out_da1 <= 0;
end
endtask
always @(posedge trigger_begin)
begin
if(triggerjudge_en)
begin
if(trigger_begin)
trigger_en <= 1;
else
trigger_en <= 0;
end
end
assign out_switch = 8'b1000_1100;
endmodule |
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发表于 2010-6-12 20:09:56
