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楼主 |
发表于 2010-10-23 20:48:49
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The following is a list of the current limitations of the model.
Comparator A :
Analog pins do not output reference voltage to the outer scheme.
Comparator A+:
Bit CASHORT is not modeled.
Bootstrap Loader :
Not present at this time.
FLASH:
Memory contents are not preserved after simulation.
Supply Voltage Supervisor:
Not present at this time. POR and PUC are not modeled. Processor just starts with appropriate delay (see datasheet).
Clock Module:
There is no frequency checking of LFXT1. You can set any value at your own risk. External Rosc influence for DCO is not modeled.
ADC 10-Bit:
The pin ADC10SR which controls conversion rate and power consumption is not modeled.
ADC 12-Bit:
The TAG_ADC12_1 Calibration TLV structure is not implemented.
Universal Serial Communication Interface, UART Mode:
IrDA data exchange is not modeled. The state of the bit UCIREN = 1 is ignored.
Generic:
- Auxiliary pins for device programming and test (TDI, TDO, TCLK, TMS, TEST, etc.) are not modeled.
- UBROF8 object file format doesn抰 allow inspect variables now. |
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