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发表于 2011-3-30 11:40:39
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5、初始化配置设计
88E6083 提供了硬件配置和软件配置两种配置方法：
 88E6083提供了多个硬件配置管脚，需要外加上下拉配置电阻，复位信号上升沿时读取配置，确定芯片初时工作状态。
表1 88E6083 硬件配置表
管脚号 管脚名 配置说明 本设计配置
全部采用1K电阻下拉，配置8个端口为自动协商
199 CONFIG_A 端口LED配置：
VSS = LED Mode 0, FEFI disabled
P0_LED0 = LED Mode 0, FEFI enabled
P0_LED1 = LED Mode 1, FEFI disabled
P0_LED2 = LED Mode 1, FEFI enabled
P1_LED0 = LED Mode 2, FEFI disabled
P1_LED1 = LED Mode 2, FEFI enabled
P1_LED2 = LED Mode 3, FEFI disabled
VDDO = LED Mode 3, FEFI enabled - default 本设计CONFIG_A连接到P1_LED2,选择LED Mode3，禁止FEFI
201 CONFIG_B VSS = No Crossover, Class A1 drivers, Energy Detect disabled
P0_LED0 = No Crossover, Class A drivers, Energy Detect enabled
P0_LED1 = No Crossover, Class B2 drivers, Energy Detect disabled
P0_LED2 = No Crossover, Class B drivers, Energy Detect enabled
P1_LED0 = Auto Crossover, Class A drivers, Energy Detect disabled
P1_LED1 = Auto Crossover, Class A drivers, Energy Detect enabled
P1_LED2 = Auto Crossover, Class B drivers, Energy Detect disabled
VDDO = Auto Crossover, Class B drivers, Energy Detect enabled -
default 本设计采用默认值，通过4.7K电阻上拉。使能Auto Crossover
121 CLK_SEL Clock frequency Select. Connect this pin to VSS if XTAL_IN
is 25 MHz. Connect this pin to VDDO or leave it unconnected
if XTAL_IN is 50 MHz. This pin must be stable before
and after Reset. 通过1K电阻下拉，选择25Mhz时钟。
116 EE_CS
/EE_1K
Low = Use 8-bit addresses (for 2K bit 93C56 & 4K bit 93C66)
High = Use 6-bit addresses (for 1K bit 93C46) 采用默认配置上拉，选择使用93C46
117 EE_DIN/
HD_FLOW_DIS
Low = Enable “forced collision” flow control on all half duplex
ports
High = Disable flow control on all half-duplex ports 采用默认配置上拉，禁止半双工模式下流控
120 ENABLE_P8
Enable Port 8. This pin is used to enable the Port 8 MII drivers
(Table 9). A high enables the Port 8 drivers. A low disables Port 8
and its drivers (i.e., they are tri-stated). 采用4.7K电阻上拉，使用P8端口。
P8_OUTD3
/P8_MODE3
/P8_MODE3
P8_OUTD3
/P8_MODE3 P8端口模式配置，具体配置说明见下图。 配置为[1010],配置P8工作在100M 全双工MAC下。
151 DISABLE_P9 Disable Port 9. This pin is used to disable Port 9’s MII drivers
(Table 9). A high disables Port 9’s drivers (i.e., they are tristated).
A low enables Port 9 and its drivers. 采用1K电阻下拉，使用P9端口。
P9_OUTD3
/P9_MODE3
P9_OUTD3
/P9_MODE3 P8端口模式配置，具体配置说明见表二。 配置为[1111],配置P9工作在100M 全双工PHY模式下。
SW_MODE1
SW_MODE0
1 0 Description
0 0 CPU attached mode – ports come up disabled1
0 1 Reserved
1 0 Stand-alone mode – ports come up enabled – ignore EEPROM
1 1 EEPROM attached mode – EEPROM defined port states2
做上下拉兼容设计，调试时采用Stand－alone模式，正式使用时采用CPU管理模式
High = disable flow control on all full-duplex ports
Low = enable IEEE 802.3x Pause based flow control on all supported
full-duplex ports
采用4.7K电阻上拉，禁止全双工流控 |
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发表于 2010-11-10 23:12:32
