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发表于 2011-6-16 09:40:55
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回复【3楼】fsclub 绿林好汉
系统频率的一半。
你没试过更高频率为何说不可?
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如果系统工作频率16M,那么I/O的时钟也就是16M,T0硬件每个时钟检测一次输入的变化,一次高/一次低,需要2个CLK,所以外部输入信号的最高频率8M。
这个是同步模式,在手册中有解释。要证明吗?
Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5.
我说理论上为系统频率的一半,实际上都做不到,手册上的建议为 系统频率/2.5 !
你愿意去测试吗?我可不用测试。你有本事你去测试。
如果你使用了其它外接的电路,如分频器等,是另外一会事 |
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