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module bjj(
Reset,
Clock_8MHz,
in,in1,in2,
Pulse,
cc,cs,led
);
input Reset,in,in1,in2;
input Clock_8MHz;
output Pulse,cc,cs;
output [7:0]led;
reg [16:0] Acceleration;//加速度
reg [15:0] Speed;//速率,速度
reg [23:0] Sum;//总数
wire F_65536Hz;
reg [15:0] WIRE_1;
wire F_1Hz;
reg [15:0] WIRE_4;
reg [15:0] WIRE_5;
reg WIRE_6;
reg cc;
reg m0,m2;
wire [7:0]led;
assign led=WIRE_6;
always @(posedge Clock_8MHz )
begin
if(in1==0&&m0==1)begin
m0=1'b0;
cc<=~cc;
Acceleration<=20000;
Speed<=50;
Sum<=2000000;
end
if(in1==1&&m0==0)m0=1'b1;
end
/////////////////////////////////////////
reg [22:0] CNT;
//全局时钟经过100分频后得到65536Hz时钟信号
always @(posedge Clock_8MHz or negedge in)
begin
//if(Reset == 1'b0)
if(in == 1'b0)
CNT <= 23'b0;
else
begin
if(CNT < 23'b11111111111111111111111) //实际中的分频值
CNT <= CNT + 23'b1;
else
CNT <= 23'b0;
end
end
/*以下是实际系统的值*/
assign F_65536Hz = CNT[6];
assign F_1Hz = CNT[22];
///////////////////////////////////////////////////
always @(posedge F_65536Hz or negedge in)
begin
if(in == 1'b0)
WIRE_1<=16'b0;
else begin if(WIRE_1 < 16'b1111111111111111)
WIRE_1 <= WIRE_1 + 16'b1;
else
WIRE_1 <= 16'b0;
end
end
/////////////////////////////////////////////////
always @(Reset,WIRE_1,WIRE_4,in)
begin
//if(Reset == 1'b0)
if(in == 1'b0)
WIRE_4 <= 16'b0;
else
begin
if(WIRE_1[0] == 1'b1)
WIRE_4[15] <= 1'b1;
else
WIRE_4[15] <= 1'b0;
if(WIRE_1[1:0] == 2'b10)
WIRE_4[14] <= 1'b1;
else
WIRE_4[14] <= 1'b0;
if(WIRE_1[2:0] == 3'b100)
WIRE_4[13] <= 1'b1;
else
WIRE_4[13] <= 1'b0;
if(WIRE_1[3:0] == 4'b1000)
WIRE_4[12] <= 1'b1;
else
WIRE_4[12] <= 1'b0;
if(WIRE_1[4:0] == 5'b10000)
WIRE_4[11] <= 1'b1;
else
WIRE_4[11] <= 1'b0;
if(WIRE_1[5:0] == 6'b100000)
WIRE_4[10] <= 1'b1;
else
WIRE_4[10] <= 1'b0;
if(WIRE_1[6:0] == 7'b1000000)
WIRE_4[9] <= 1'b1;
else
WIRE_4[9] <= 1'b0;
if(WIRE_1[7:0] == 8'b10000000)
WIRE_4[8] <= 1'b1;
else
WIRE_4[8] <= 1'b0;
if(WIRE_1[8:0] == 9'b100000000)
WIRE_4[7] <= 1'b1;
else
WIRE_4[7] <= 1'b0;
if(WIRE_1[9:0] == 10'b1000000000)
WIRE_4[6] <= 1'b1;
else
WIRE_4[6] <= 1'b0;
if(WIRE_1[10:0] == 11'b10000000000)
WIRE_4[5] <= 1'b1;
else
WIRE_4[5] <= 1'b0;
if(WIRE_1[11:0] == 12'b100000000000)
WIRE_4[4] <= 1'b1;
else
WIRE_4[4] <= 1'b0;
if(WIRE_1[12:0] == 13'b1000000000000)
WIRE_4[3] <= 1'b1;
else
WIRE_4[3] <= 1'b0;
if(WIRE_1[13:0] == 14'b10000000000000)
WIRE_4[2] <= 1'b1;
else
WIRE_4[2] <= 1'b0;
if(WIRE_1[14:0] == 15'b100000000000000)
WIRE_4[1] <= 1'b1;
else
WIRE_4[1] <= 1'b0;
if(WIRE_1[15:0] == 16'b1000000000000000)
WIRE_4[0] <= 1'b1;
else
WIRE_4[0] <= 1'b0;
end
end
/////////////////////////////////////////////
initial
begin
WIRE_5 <= Speed;
end
always @(posedge F_1Hz or negedge in)
begin
if(in == 1'b0)
//if(Reset == 1'b0)
WIRE_5 <= 16'b0;
else
begin
if(Acceleration[16] == 1'b0) //加速度为正
begin
if((WIRE_5 + Acceleration[15:0]) < 16'b1111111111111111)
//加速，且速度不超过65535
WIRE_5 <= WIRE_5 + Acceleration[15:0];
else
//速度超过65535，直接固定在65535
WIRE_5 <= 16'b1111111111111111;
end
else if(Acceleration[16] == 1'b1) //加速度为负
begin
if((WIRE_5 - Acceleration[15:0]) > 16'b0)
//减速，且速度不小于0
WIRE_5 <= WIRE_5 - Acceleration[15:0];
else
//减速，且速度小于0,直接固定在0，即停止
WIRE_5 <= 16'b0;
end
end
end
///////////////////////////////////////////////////////
reg [15:0] pulse_1;
reg [3:0] cnt;
always @(Reset,F_65536Hz,WIRE_4,WIRE_5,pulse_1,cnt,in)
begin
//if(Reset == 1'b0)
if(in == 1'b0)
WIRE_6 <= 1'b0;
else
begin
for(cnt = 4'b0;cnt < 4'b1111;cnt = cnt + 4'b1)
begin
pulse_1[cnt] <= WIRE_5[cnt] && WIRE_4[cnt] && F_65536Hz;
if(cnt == 4'b1111) cnt <= 4'b0;
end
WIRE_6 <= pulse_1[0] || pulse_1[1] ||
pulse_1[2] || pulse_1[3] ||
pulse_1[4] || pulse_1[5] ||
pulse_1[6] || pulse_1[7] ||
pulse_1[8] || pulse_1[9] ||
pulse_1[10] || pulse_1[11] ||
pulse_1[12] || pulse_1[13] ||
pulse_1[14] || pulse_1[15];
end
end
//////////////////////////////////////////////////////////////
reg [23:0] step_counter;
reg out_control;
always @(posedge WIRE_6 or negedge in)
begin
//if(Reset == 1'b0)
if(in == 1'b0)
begin
step_counter <= 24'b0;
out_control <= 1'b0;
end
else
begin
if(step_counter == (Sum - 24'b1))
out_control <= 1'b0;
else if(step_counter == 24'b111111111111111111111111)
step_counter <= 24'b0;
else
begin
step_counter <= step_counter + 24'b1;
out_control <= 1'b1;
end
end
end
assign Pulse = WIRE_6 && out_control;
endmodule
只有加速、高速、没有减速的控制过程大家帮忙看一下 |
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发表于 2011-8-13 06:09:56
