ARM菜鸟改造令人烦恼的头文件AT91SAM7S64.H

hotpower · 发表于 2005-9-15 13:24:49

ARM菜鸟改造令人烦恼的头文件AT91SAM7S64.H

hotpower 发表于 2005-8-24 23:30 ARM 论坛 ←返回版面举报该贴

/*-----------------------------------------------------------------------------

         ARM菜鸟改造令人烦恼的头文件AT91SAM7S64.H

改造原因: 令人烦恼的*AT91C_,使书写更加符合日常习惯.结构及结构指针的写法很烦人.

      虽然可能优化代码,但本头文件效率相同.

      其他AT91下列有PIO.H等头文件,但对AT91SAM7S64不太适合

文件名: AT91SAM7S64DEF.H

HotPower@126.com 2005.8.24  于西安大雁塔村队部  (首次修改)

-------------------------------------------------------------------------------*/

#include <AT91SAM7S64.H>

#ifndef AT91SAM7S64DEF_H

#define AT91SAM7S64DEF_H

// *****************************************************************************

//             REGISTER ADDRESS DEFINITION FOR AT91SAM7S64

// *****************************************************************************

// ========== Register definition for SYSC peripheral ==========

#define SYSC_VRPM    (*AT91C_SYSC_SYSC_VRPM) // (SYSC) Voltage Regulator Power Mode Register

// ========== Register definition for AIC peripheral ==========

#define AIC_ICCR       (*AT91C_AIC_ICCR) // (AIC) Interrupt Clear Command Register

#define AIC_IECR       (*AT91C_AIC_IECR) // (AIC) Interrupt Enable Command Register

#define AIC_SMR       (*AT91C_AIC_SMR) // (AIC) Source Mode Register

#define AIC_ISCR       (*AT91C_AIC_ISCR) // (AIC) Interrupt Set Command Register

#define AIC_EOICR    (*AT91C_AIC_EOICR) // (AIC) End of Interrupt Command Register

#define AIC_DCR       (*AT91C_AIC_DCR) // (AIC) Debug Control Register (Protect)

#define AIC_FFER       (*AT91C_AIC_FFER) // (AIC) Fast Forcing Enable Register

#define AIC_SVR       (*AT91C_AIC_SVR) // (AIC) Source Vector Register

#define AIC_SPU       (*AT91C_AIC_SPU) // (AIC) Spurious Vector Register

#define AIC_FFDR       (*AT91C_AIC_FFDR) // (AIC) Fast Forcing Disable Register

#define AIC_FVR       (*AT91C_AIC_FVR) // (AIC) FIQ Vector Register

#define AIC_FFSR       (*AT91C_AIC_FFSR) // (AIC) Fast Forcing Status Register

#define AIC_IMR       (*AT91C_AIC_IMR) // (AIC) Interrupt Mask Register

#define AIC_ISR       (*AT91C_AIC_ISR) // (AIC) Interrupt Status Register

#define AIC_IVR       (*AT91C_AIC_IVR) // (AIC) IRQ Vector Register

#define AIC_IDCR       (*AT91C_AIC_IDCR) // (AIC) Interrupt Disable Command Register

#define AIC_CISR       (*AT91C_AIC_CISR) // (AIC) Core Interrupt Status Register

#define AIC_IPR       (*AT91C_AIC_IPR) // (AIC) Interrupt Pending Register

// ========== Register definition for DBGU peripheral ==========

#define DBGU_C2R       (*AT91C_DBGU_C2R) // (DBGU) Chip ID2 Register

#define DBGU_THR       (*AT91C_DBGU_THR) // (DBGU) Transmitter Holding Register

#define DBGU_CSR       (*AT91C_DBGU_CSR) // (DBGU) Channel Status Register

#define DBGU_CSR       (*AT91C_DBGU_CSR) // (DBGU) Interrupt Disable Register

#define DBGU_CSR       (*AT91C_DBGU_CSR) // (DBGU) Mode Register

#define DBGU_FNTR    (*AT91C_DBGU_FNTR) // (DBGU) Force NTRST Register

#define DBGU_C1R       (*AT91C_DBGU_C1R) // (DBGU) Chip ID1 Register

#define DBGU_BRGR    (*AT91C_DBGU_BRGR) // (DBGU) Baud Rate Generator Register

#define DBGU_RHR       (*AT91C_DBGU_RHR) // (DBGU) Receiver Holding Register

#define DBGU_IMR       (*AT91C_DBGU_IMR) // (DBGU) Interrupt Mask Register

#define DBGU_IER       (*AT91C_DBGU_IER) // (DBGU) Interrupt Enable Register

#define DBGU_CR       (*AT91C_DBGU_CR) // (DBGU) Control Register

// ========== Register definition for PDC_DBGU peripheral ==========

#define DBGU_TNCR    (*AT91C_DBGU_TNCR) // (PDC_DBGU) Transmit Next Counter Register

#define DBGU_RNCR    (*AT91C_DBGU_RNCR) // (PDC_DBGU) Receive Next Counter Register

#define DBGU_PTCR    (*AT91C_DBGU_PTCR) // (PDC_DBGU) PDC Transfer Control Register

#define DBGU_PTSR    (*AT91C_DBGU_PTSR) // (PDC_DBGU) PDC Transfer Status Register

#define DBGU_RCR       (*AT91C_DBGU_RCR) // (PDC_DBGU) Receive Counter Register

#define DBGU_TCR       (*AT91C_DBGU_TCR) // (PDC_DBGU) Transmit Counter Register

#define DBGU_RPR       (*AT91C_DBGU_RPR) // (PDC_DBGU) Receive Pointer Register

#define DBGU_RPR       (*AT91C_DBGU_RPR) // (PDC_DBGU) Transmit Pointer Register

#define DBGU_RNPR    (*AT91C_DBGU_RNPR) // (PDC_DBGU) Receive Next Pointer Register

#define DBGU_TNPR    (*AT91C_DBGU_TNPR) // (PDC_DBGU) Transmit Next Pointer Register

// ========== Register definition for PIOA peripheral ==========

#define PIO_IMR       (*AT91C_PIOA_IMR) // (PIOA) Interrupt Mask Register

#define PIO_IER       (*AT91C_PIOA_IER) // (PIOA) Interrupt Enable Register

#define PIO_OWDR       (*AT91C_PIOA_OWDR) // (PIOA) Output Write Disable Register

#define PIO_ISR       (*AT91C_PIOA_ISR) // (PIOA) Interrupt Status Register

#define PIO_PPUDR    (*AT91C_PIOA_PPUDR) // (PIOA) Pull-up Disable Register

#define PIO_MDSR       (*AT91C_PIOA_MDSR) // (PIOA) Multi-driver Status Register

#define PIO_MDER       (*AT91C_PIOA_MDER) // (PIOA) Multi-driver Enable Register

#define PIO_PER       (*AT91C_PIOA_PER) // (PIOA) PIO Enable Register

#define PIO_PSR       (*AT91C_PIOA_PSR) // (PIOA) PIO Status Register

#define PIO_OER       (*AT91C_PIOA_OER) // (PIOA) Output Enable Register

#define PIO_BSR       (*AT91C_PIOA_BSR) // (PIOA) Select B Register

#define PIO_PPUER    (*AT91C_PIOA_PPUER) // (PIOA) Pull-up Enable Register

#define PIO_MDDR       (*AT91C_PIOA_MDDR) // (PIOA) Multi-driver Disable Register

#define PIO_PDR       (*AT91C_PIOA_PDR) // (PIOA) PIO Disable Register

#define PIO_ODR       (*AT91C_PIOA_ODR) // (PIOA) Output Disable Registerr

#define PIO_IFDR       (*AT91C_PIOA_IFDR) // (PIOA) Input Filter Disable Register

#define PIO_ABSR       (*AT91C_PIOA_ABSR) // (PIOA) AB Select Status Register

#define PIO_ASR       (*AT91C_PIOA_ASR) // (PIOA) Select A Register

#define PIO_PPUSR    (*AT91C_PIOA_PPUSR8) // (PIOA) Pad Pull-up Status Register

#define PIO_ODSR       (*AT91C_PIOA_ODSR) // (PIOA) Output Data Status Register

#define PIO_SODR       (*AT91C_PIOA_SODR) // (PIOA) Set Output Data Register

#define PIO_IFSR       (*AT91C_PIOA_IFSR) // (PIOA) Input Filter Status Register

#define PIO_IFER       (*AT91C_PIOA_IFER) // (PIOA) Input Filter Enable Register

#define PIO_OSR       (*AT91C_PIOA_OSR) // (PIOA) Output Status Register

#define PIO_IDR       (*AT91C_PIOA_IDR) // (PIOA) Interrupt Disable Register

#define PIO_PDSR       (*AT91C_PIOA_PDSR) // (PIOA) Pin Data Status Register

#define PIO_CODR       (*AT91C_PIOA_CODR) // (PIOA) Clear Output Data Register

#define PIO_OWSR       (*AT91C_PIOA_OWSR) // (PIOA) Output Write Status Register

#define PIO_OWER       (*AT91C_PIOA_OWER) // (PIOA) Output Write Enable Register

// ========== Register definition for CKGR peripheral ==========

#define CKGR_PLLR    (*AT91C_CKGR_PLLR) // (CKGR) PLL Register

#define CKGR_MCFR    (*AT91C_CKGR_MCFR) // (CKGR) Main Clock  Frequency Register

#define CKGR_MOR       (*AT91C_CKGR_MOR) // (CKGR) Main Oscillator Register

// ========== Register definition for PMC peripheral ==========

#define PMC_SCSR       (*AT91C_PMC_SCSR) // (PMC) System Clock Status Register

#define PMC_SCER       (*AT91C_PMC_SCER) // (PMC) System Clock Enable Register

#define PMC_IMR       (*AT91C_PMC_IMR) // (PMC) Interrupt Mask Register

#define PMC_IDR       (*AT91C_PMC_IDR) // (PMC) Interrupt Disable Register

#define PMC_PCDR       (*AT91C_PMC_PCDR) // (PMC) Peripheral Clock Disable Register

#define PMC_SCDR       (*AT91C_PMC_SCDR) // (PMC) System Clock Disable Register

#define PMC_SR       (*AT91C_PMC_SR) // (PMC) Status Register

#define PMC_IER       (*AT91C_PMC_IER) // (PMC) Interrupt Enable Register

#define PMC_MCKR       (*AT91C_PMC_MCKR) // (PMC) Master Clock Register

#define PMC_MOR       (*AT91C_PMC_MOR) // (PMC) Main Oscillator Register

#define PMC_PCER       (*AT91C_PMC_PCER) // (PMC) Peripheral Clock Enable Register

#define PMC_PCSR       (*AT91C_PMC_PCSR) // (PMC) Peripheral Clock Status Register

#define PMC_PLLR       (*AT91C_PMC_PLLR) // (PMC) PLL Register

#define PMC_MCFR       (*AT91C_PMC_MCFR) // (PMC) Main Clock  Frequency Register

#define PMC_PCKR       (*AT91C_PMC_PCKR) // (PMC) Programmable Clock Register

// ========== Register definition for RSTC peripheral ==========

#define RSTC_SR       (*AT91C_RSTC_RSR) // (RSTC) Reset Status Register

#define RSTC_MR       (*AT91C_RSTC_RMR) // (RSTC) Reset Mode Register

#define RSTC_CR       (*AT91C_RSTC_RCR) // (RSTC) Reset Control Register

// ========== Register definition for RTTC peripheral ==========

#define RTT_SR       (*AT91C_RTTC_RTSR) // (RTTC) Real-time Status Register

#define RTT_AR       (*AT91C_RTTC_RTAR) // (RTTC) Real-time Alarm Register

#define RTT_VR       (*AT91C_RTTC_RTVR) // (RTTC) Real-time Value Register

#define RTT_MR       (*AT91C_RTTC_RTMR) // (RTTC) Real-time Mode Register

// ========== Register definition for PITC peripheral ==========

#define PIT_PIIR       (*AT91C_PITC_PIIR) // (PITC) Period Interval Image Register

#define PIT_SR       (*AT91C_PITC_PISR) // (PITC) Period Interval Status Register

#define PIT_PIVR       (*AT91C_PITC_PIVR) // (PITC) Period Interval Value Register

#define PIT_MR       (*AT91C_PITC_PIMR) // (PITC) Period Interval Mode Register

// ========== Register definition for WDTC peripheral ==========

#define WDT_MR       (*AT91C_WDTC_WDMR) // (WDTC) Watchdog Mode Register

#define WDT_SR       (*AT91C_WDTC_WDSR) // (WDTC) Watchdog Status Register

#define WDT_CR       (*AT91C_WDTC_WDCR) // (WDTC) Watchdog Control Register

// ========== Register definition for MC peripheral ==========

#define MC_FCR       (*AT91C_MC_FCR) // (MC) MC Flash Command Register

#define MC_ASR       (*AT91C_MC_ASR) // (MC) MC Abort Status Register

#define MC_FSR       (*AT91C_MC_FSR) // (MC) MC Flash Status Register

#define MC_FMR       (*AT91C_MC_FMR) // (MC) MC Flash Mode Register

#define MC_AASR       (*AT91C_MC_AASR) // (MC) MC Abort Address Status Register

#define MC_RCR       (*AT91C_MC_RCR) // (MC) MC Remap Control Register

// ========== Register definition for PDC_SPI peripheral ==========

#define SPI_PTCR       (*AT91C_SPI_PTCR) // (PDC_SPI) PDC Transfer Control Register

#define SPI_TNPR       (*AT91C_SPI_TNPR) // (PDC_SPI) Transmit Next Pointer Register

#define SPI_RNPR       (*AT91C_SPI_RNPR) // (PDC_SPI) Receive Next Pointer Register

#define SPI_TPR       (*AT91C_SPI_TPR) // (PDC_SPI) Transmit Pointer Register

#define SPI_RPR       (*AT91C_SPI_RPR) // (PDC_SPI) Receive Pointer Register

#define SPI_PTSR       (*AT91C_SPI_PTSR) // (PDC_SPI) PDC Transfer Status Register

#define SPI_TNCR       (*AT91C_SPI_TNCR) // (PDC_SPI) Transmit Next Counter Register

#define SPI_RNCR       (*AT91C_SPI_RNCR) // (PDC_SPI) Receive Next Counter Register

#define SPI_TCR       (*AT91C_SPI_TCR) // (PDC_SPI) Transmit Counter Register

#define SPI_RCR       (*AT91C_SPI_RCR) // (PDC_SPI) Receive Counter Register

// ========== Register definition for SPI peripheral ==========

#define SPI_CSR       (*AT91C_SPI_CSR) // (SPI) Chip Select Register

#define SPI_IDR       (*AT91C_SPI_IDR) // (SPI) Interrupt Disable Register

#define SPI_SR       (*AT91C_SPI_SR) // (SPI) Status Register

#define SPI_RDR       (*AT91C_SPI_RDR) // (SPI) Receive Data Register

#define SPI_CR       (*AT91C_SPI_CR) // (SPI) Control Register

#define SPI_IMR       (*AT91C_SPI_IMR) // (SPI) Interrupt Mask Register

#define SPI_IER       (*AT91C_SPI_IER) // (SPI) Interrupt Enable Register

#define SPI_TDR       (*AT91C_SPI_TDR) // (SPI) Transmit Data Register

#define SPI_MR       (*AT91C_SPI_MR) // (SPI) Mode Register

// ========== Register definition for PDC_ADC peripheral ==========

#define ADC_PTCR       (*AT91C_ADC_PTCR) // (PDC_ADC) PDC Transfer Control Register

#define ADC_TNPR       (*AT91C_ADC_TNPR) // (PDC_ADC) Transmit Next Pointer Register

#define ADC_RNPR       (*AT91C_ADC_RNPR) // (PDC_ADC) Receive Next Pointer Register

#define ADC_TPR       (*AT91C_ADC_TPR) // (PDC_ADC) Transmit Pointer Register

#define ADC_RPR       (*AT91C_ADC_RPR) // (PDC_ADC) Receive Pointer Register

#define ADC_PTSR       (*AT91C_ADC_PTSR) // (PDC_ADC) PDC Transfer Status Register

#define ADC_TNCR       (*AT91C_ADC_TNCR) // (PDC_ADC) Transmit Next Counter Register

#define ADC_RNCR       (*AT91C_ADC_RNCR) // (PDC_ADC) Receive Next Counter Register

#define ADC_TCR       (*AT91C_ADC_TCR) // (PDC_ADC) Transmit Counter Register

#define ADC_RCR       (*AT91C_ADC_RCR) // (PDC_ADC) Receive Counter Register

// ========== Register definition for ADC peripheral ==========

#define ADC_IMR       (*AT91C_ADC_IMR) // (ADC) ADC Interrupt Mask Register

#define ADC_CDR4       (*AT91C_ADC_CDR4) // (ADC) ADC Channel Data Register 4

#define ADC_CDR2       (*AT91C_ADC_CDR2) // (ADC) ADC Channel Data Register 2

#define ADC_CDR0       (*AT91C_ADC_CDR0) // (ADC) ADC Channel Data Register 0

#define ADC_CDR7       (*AT91C_ADC_CDR7) // (ADC) ADC Channel Data Register 7

#define ADC_CDR1       (*AT91C_ADC_CDR1) // (ADC) ADC Channel Data Register 1

#define ADC_CDR3       (*AT91C_ADC_CDR3) // (ADC) ADC Channel Data Register 3

#define ADC_CDR5       (*AT91C_ADC_CDR5) // (ADC) ADC Channel Data Register 5

#define ADC_MR       (*AT91C_ADC_MR) // (ADC) ADC Mode Register

#define ADC_CDR6       (*AT91C_ADC_CDR6) // (ADC) ADC Channel Data Register 6

#define ADC_CR       (*AT91C_ADC_CR) // (ADC) ADC Control Register

#define ADC_CHER       (*AT91C_ADC_CHER) // (ADC) ADC Channel Enable Register

#define ADC_CHSR       (*AT91C_ADC_CHSR) // (ADC) ADC Channel Status Register

#define ADC_IER       (*AT91C_ADC_IER) // (ADC) ADC Interrupt Enable Register

#define ADC_SR       (*AT91C_ADC_SR) // (ADC) ADC Status Register

#define ADC_CHDR       (*AT91C_ADC_CHDR) // (ADC) ADC Channel Disable Register

#define ADC_IDR       (*AT91C_ADC_IDR) // (ADC) ADC Interrupt Disable Register

#define ADC_LCDR       (*AT91C_ADC_LCDR) // (ADC) ADC Last Converted Data Register

// ========== Register definition for PDC_SSC peripheral ==========

#define SSC_PTCR       (*AT91C_SSC_PTCR) // (PDC_SSC) PDC Transfer Control Register

#define SSC_TNPR       (*AT91C_SSC_TNPR) // (PDC_SSC) Transmit Next Pointer Register

#define SSC_RNPR       (*AT91C_SSC_RNPR) // (PDC_SSC) Receive Next Pointer Register

#define SSC_TPR       (*AT91C_SSC_TPR) // (PDC_SSC) Transmit Pointer Register

#define SSC_RPR       (*AT91C_SSC_RPR) // (PDC_SSC) Receive Pointer Register

#define SSC_PTSR       (*AT91C_SSC_PTSR) // (PDC_SSC) PDC Transfer Status Register

#define SSC_TNCR       (*AT91C_SSC_TNCR) // (PDC_SSC) Transmit Next Counter Register

#define SSC_RNCR       (*AT91C_SSC_RNCR) // (PDC_SSC) Receive Next Counter Register

#define SSC_TCR       (*AT91C_SSC_TCR) // (PDC_SSC) Transmit Counter Register

#define SSC_RCR       (*AT91C_SSC_RCR) // (PDC_SSC) Receive Counter Register

// ========== Register definition for SSC peripheral ==========

#define SSC_RFMR       (*AT91C_SSC_RFMR) // (SSC) Receive Frame Mode Register

#define SSC_CMR       (*AT91C_SSC_CMR) Clock Mode Register

#define SSC_IDR       (*AT91C_SSC_IDR) // (SSC) Interrupt Disable Register

#define SSC_SR       (*AT91C_SSC_SR) // (SSC) Status Register

#define SSC_RC0R       (*AT91C_SSC_RC0R) // (SSC) Receive Compare 0 Register

#define SSC_RSHR       (*AT91C_SSC_RSHR) // (SSC) Receive Sync Holding Register

#define SSC_RHR       (*AT91C_SSC_RHR) // (SSC) Receive Holding Register

#define SSC_TCMR       (*AT91C_SSC_TCMR) // (SSC) Transmit Clock Mode Register

#define SSC_RCMR       (*AT91C_SSC_RCMR) // (SSC) Receive Clock ModeRegister

#define SSC_CR       (*AT91C_SSC_CR) // (SSC) Control Register

#define SSC_IMR       (*AT91C_SSC_IMR) // (SSC) Interrupt Mask Register

#define SSC_IER       (*AT91C_SSC_IER) // (SSC) Interrupt Enable Register

#define SSC_RC1R       (*AT91C_SSC_RC1R) // (SSC) Receive Compare 1 Register

#define SSC_TSHR       (*AT91C_SSC_TSHR) // (SSC) Transmit Sync Holding Register

#define SSC_THR       (*AT91C_SSC_THR) // (SSC) Transmit Holding Register

#define SSC_TFMR       (*AT91C_SSC_TFMR) // (SSC) Transmit Frame Mode Register

// ========== Register definition for PDC_US1 peripheral ==========

#define US1_PTSR       (*AT91C_US1_PTSR) // (PDC_US1) PDC Transfer Status Register

#define US1_TNCR       (*AT91C_US1_TNCR) // (PDC_US1) Transmit Next Counter Register

#define US1_RNCR       (*AT91C_US1_RNCR) // (PDC_US1) Receive Next Counter Register

#define US1_TCR       (*AT91C_US1_TCR) // (PDC_US1) Transmit Counter Register

#define US1_RCR       (*AT91C_US1_RCR) // (PDC_US1) Receive Counter Register

#define US1_PTCR       (*AT91C_US1_PTCR) // (PDC_US1) PDC Transfer Control Register

#define US1_TNPR       (*AT91C_US1_TNPR) // (PDC_US1) Transmit Next Pointer Register

#define US1_RNPR       (*AT91C_US1_RNPR) // (PDC_US1) Receive Next Pointer Register

#define US1_TPR       (*AT91C_US1_TPR) // (PDC_US1) Transmit Pointer Register

#define US1_RPR       (*AT91C_US1_RPR) // (PDC_US1) Receive Pointer Register

// ========== Register definition for US1 peripheral ==========

#define US1_XXR       (*AT91C_US1_XXR) // (US1) XON_XOFF Register

#define US1_RHR       (*AT91C_US1_RHR) // (US1) Receiver Holding Register

#define US1_IMR       (*AT91C_US1_IMR) // (US1) Interrupt Mask Register

#define US1_IER       (*AT91C_US1_IER) // (US1) Interrupt Enable Register

#define US1_CR       (*AT91C_US1_CR) // (US1) Control Register

#define US1_RTOR       (*AT91C_US1_RTOR) // (US1) Receiver Time-out Register

#define US1_THR       (*AT91C_US1_THR) // (US1) Transmitter Holding Register

#define US1_CSR       (*AT91C_US1_CSR) // (US1) Channel Status Register

#define US1_IDR       (*AT91C_US1_IDR) // (US1) Interrupt Disable Register

#define US1_FIDI       (*AT91C_US1_FIDI) // (US1) FI_DI_Ratio Register

#define US1_BRGR       (*AT91C_US1_BRGR) // (US1) Baud Rate Generator Register

#define US1_TTGR       (*AT91C_US1_TTGR) // (US1) Transmitter Time-guard Register

#define US1_IF       (*AT91C_US1_IF) // (US1) IRDA_FILTER Register

#define US1_NER       (*AT91C_US1_NER) // (US1) Nb Errors Register

#define US1_MR       (*AT91C_US1_MR) // (US1) Mode Register

// ========== Register definition for PDC_US0 peripheral ==========

#define US0_PTCR       (*AT91C_US0_PTCR) // (PDC_US0) PDC Transfer Control Register

#define US0_TNPR       (*AT91C_US0_TNPR) // (PDC_US0) Transmit Next Pointer Register

#define US0_RNPR       (*AT91C_US0_RNPR) // (PDC_US0) Receive Next Pointer Register

#define US0_TPR       (*AT91C_US0_TPR) // (PDC_US0) Transmit Pointer Register

#define US0_RPR       (*AT91C_US0_RPR) // (PDC_US0) Receive Pointer Register

#define US0_PTSR       (*AT91C_US0_PTSR) // (PDC_US0) PDC Transfer Status Register

#define US0_TNCR       (*AT91C_US0_TNCR) // (PDC_US0) Transmit Next Counter Register

#define US0_RNCR       (*AT91C_US0_RNCR) // (PDC_US0) Receive Next Counter Register

#define US0_TCR       (*AT91C_US0_TCR) // (PDC_US0) Transmit Counter Register

#define US0_RCR       (*AT91C_US0_RCR) // (PDC_US0) Receive Counter Register

// ========== Register definition for US0 peripheral ==========

#define US0_TTGR       (*AT91C_US0_TTGR) // (US0) Transmitter Time-guard Register

#define US0_BRGR       (*AT91C_US0_BRGR) // (US0) Baud Rate Generator Register

#define US0_RHR       (*AT91C_US0_RHR) // (US0) Receiver Holding Register

#define US0_IMR       (*AT91C_US0_IMR) // (US0) Interrupt Mask Register

#define US0_NER       (*AT91C_US0_NER) // (US0) Nb Errors Register

#define US0_RTOR       (*AT91C_US0_RTOR) // (US0) Receiver Time-out Register

#define US0_XXR       (*AT91C_US0_XXR) // (US0) XON_XOFF Register

#define US0_FIDI       (*AT91C_US0_FIDI) // (US0) FI_DI_Ratio Register

#define US0_CR       (*AT91C_US0_CR) // (US0) Control Register

#define US0_IER       (*AT91C_US0_IER) // (US0) Interrupt Enable Register

#define US0_IF       (*AT91C_US0_IF) // (US0) IRDA_FILTER Register

#define US0_MR       (*AT91C_US0_MR) // (US0) Mode Register

#define US0_IDR       (*AT91C_US0_IDR) // (US0) Interrupt Disable Register

#define US0_CSR       (*AT91C_US0_CSR) // (US0) Channel Status Register

#define US0_THR       (*AT91C_US0_THR) // (US0) Transmitter Holding Register

// ========== Register definition for TWI peripheral ==========

#define TWI_RHR       (*AT91C_TWI_RHR) // (TWI) Receive Holding Register

#define TWI_IDR       (*AT91C_TWI_IDR) // (TWI) Interrupt Disable Register

#define TWI_SR       (*AT91C_TWI_SR) // (TWI) Status Register

#define TWI_CWGR       (*AT91C_TWI_CWGR) // (TWI) Clock Waveform Generator Register

#define TWI_SMR       (*AT91C_TWI_SMR) // (TWI) Slave Mode Register

#define TWI_CR       (*AT91C_TWI_CR) // (TWI) Control Register

#define TWI_THR       (*AT91C_TWI_THR) // (TWI) Transmit Holding Register

#define TWI_IMR       (*AT91C_TWI_IMR) // (TWI) Interrupt Mask Register

#define TWI_IER       (*AT91C_TWI_IER) // (TWI) Interrupt Enable Register

#define TWI_IADR       (*AT91C_TWI_IADR) // (TWI) Internal Address Register

#define TWI_MMR       (*AT91C_TWI_MMR) // (TWI) Master Mode Register

// ========== Register definition for TC2 peripheral ==========

#define TC2_IMR       (*AT91C_TC2_IMR) // (TC2) Interrupt Mask Register

#define TC2_IER       (*AT91C_TC2_IER) // (TC2) Interrupt Enable Register

#define TC2_RC       (*AT91C_TC2_RC) // (TC2) Register C

#define TC2_RA       (*AT91C_TC2_RA) // (TC2) Register A

#define TC2_CMR       (*AT91C_TC2_CMR) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)

#define TC2_IDR       (*AT91C_TC2_IDR) // (TC2) Interrupt Disable Register

#define TC2_SR       (*AT91C_TC2_SR) // (TC2) Status Register

#define TC2_RB       (*AT91C_TC2_RB) // (TC2) Register B

#define TC2_CV       (*AT91C_TC2_CV) // (TC2) Counter Value

#define TC2_CCR       (*AT91C_TC2_CCR) // (TC2) Channel Control Register

// ========== Register definition for TC1 peripheral ==========

#define TC1_IMR       (*AT91C_TC1_IMR) // (TC1) Interrupt Mask Register

#define TC1_IER       (*AT91C_TC1_IER) // (TC1) Interrupt Enable Register

#define TC1_RC       (*AT91C_TC1_RC) // (TC1) Register C

#define TC1_RA       (*AT91C_TC1_RA) // (TC1) Register A

#define TC1_CMR       (*AT91C_TC1_CMR) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)

#define TC1_IDR       (*AT91C_TC1_IDR) // (TC1) Interrupt Disable Register

#define TC1_SR       (*AT91C_TC1_SR) // (TC1) Status Register

#define TC1_RB       (*AT91C_TC1_RB) // (TC1) Register B

#define TC1_CV       (*AT91C_TC1_CV) // (TC1) Counter Value

#define TC1_CCR       (*AT91C_TC1_CCR) // (TC1) Channel Control Register

// ========== Register definition for TC0 peripheral ==========

#define TC0_IMR       (*AT91C_TC0_IMR) // (TC0) Interrupt Mask Register

#define TC0_IER       (*AT91C_TC0_IER) // (TC0) Interrupt Enable Register

#define TC0_RC       (*AT91C_TC0_RC) // (TC0) Register C

#define TC0_RA       (*AT91C_TC0_RA) // (TC0) Register A

#define TC0_CMR       (*AT91C_TC0_CMR) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)

#define TC0_IDR       (*AT91C_TC0_IDR) // (TC0) Interrupt Disable Register

#define TC0_SR       (*AT91C_TC0_SR) // (TC0) Status Register

#define TC0_RB       (*AT91C_TC0_RB) // (TC0) Register B

#define TC0_CV       (*AT91C_TC0_CV) // (TC0) Counter Value

#define TC0_CCR       (*AT91C_TC0_CCR) // (TC0) Channel Control Register

// ========== Register definition for TCB peripheral ==========

#define TCB_BMR       (*AT91C_TCB_BMR) // (TCB) TC Block Mode Register

#define TCB_BCR       (*AT91C_TCB_BCR) // (TCB) TC Block Control Register

// ========== Register definition for PWMC_CH3 peripheral ==========

#define CH3_CUPDR    (*AT91C_CH3_CUPDR) // (PWMC_CH3) Channel Update Register

#define CH3_CPRDR    (*AT91C_CH3_CPRDR) // (PWMC_CH3) Channel Period Register

#define CH3_CMR       (*AT91C_CH3_CMR) // (PWMC_CH3) Channel Mode Register

#define CH3_Reserved (*AT91C_CH3_Reserved) // (PWMC_CH3) Reserved

#define CH3_CCNTR    (*AT91C_CH3_CCNTR) // (PWMC_CH3) Channel Counter Register

#define CH3_CDTYR    (*AT91C_CH3_CDTYR) // (PWMC_CH3) Channel Duty Cycle Register

// ========== Register definition for PWMC_CH2 peripheral ==========

#define CH2_CUPDR    (*AT91C_CH2_CUPDR) // (PWMC_CH2) Channel Update Register

#define CH2_CPRDR    (*AT91C_CH2_CPRDR) // (PWMC_CH2) Channel Period Register

#define CH2_CMR       (*AT91C_CH2_CMR) // (PWMC_CH2) Channel Mode Register

#define CH2_Reserved (*AT91C_CH2_Reserved) // (PWMC_CH2) Reserved

#define CH2_CCNTR    (*AT91C_CH2_CCNTR) // (PWMC_CH2) Channel Counter Register

#define CH2_CDTYR    (*AT91C_CH2_CDTYR) // (PWMC_CH2) Channel Duty Cycle Register

// ========== Register definition for PWMC_CH1 peripheral ==========

#define CH1_CUPDR    (*AT91C_CH1_CUPDR) // (PWMC_CH1) Channel Update Register

#define CH1_CPRDR    (*AT91C_CH1_CPRDR) // (PWMC_CH1) Channel Period Register

#define CH1_CMR       (*AT91C_CH1_CMR) // (PWMC_CH1) Channel Mode Register

#define CH1_Reserved (*AT91C_CH1_Reserved) // (PWMC_CH1) Reserved

#define CH1_CCNTR    (*AT91C_CH1_CCNTR) // (PWMC_CH1) Channel Counter Register

#define CH1_CDTYR    (*AT91C_CH1_CDTYR) // (PWMC_CH1) Channel Duty Cycle Register

// ========== Register definition for PWMC_CH0 peripheral ==========

#define CH0_CUPDR    (*AT91C_CH0_CUPDR) // (PWMC_CH0) Channel Update Register

#define CH0_CPRDR    (*AT91C_CH0_CPRDR) // (PWMC_CH0) Channel Period Register

#define CH0_CMR       (*AT91C_CH0_CMR) // (PWMC_CH0) Channel Mode Register

#define CH0_Reserved (*AT91C_CH0_Reserved) // (PWMC_CH0) Reserved

#define CH0_CCNTR    (*AT91C_CH0_CCNTR) // (PWMC_CH0) Channel Counter Register

#define CH0_CDTYR    (*AT91C_CH0_CDTYR) // (PWMC_CH0) Channel Duty Cycle Register

// ========== Register definition for PWMC peripheral ==========

#define PWMC_VR       (*AT91C_PWMC_VR) // (PWMC) PWMC Version Register

#define PWMC_ISR       (*AT91C_PWMC_ISR) // (PWMC) PWMC Interrupt Status Register

#define PWMC_IDR       (*AT91C_PWMC_IDR) // (PWMC) PWMC Interrupt Disable Register

#define PWMC_SR       (*AT91C_PWMC_SR) // (PWMC) PWMC Status Register

#define PWMC_ENA       (*AT91C_PWMC_ENA) // (PWMC) PWMC Enable Register

#define PWMC_IMR       (*AT91C_PWMC_IMR) // (PWMC) PWMC Interrupt Mask Register

#define PWMC_MR       (*AT91C_PWMC_MR) // (PWMC) PWMC Mode Register

#define PWMC_DIS       (*AT91C_PWMC_DIS) // (PWMC) PWMC Disable Register

#define PWMC_IER       (*AT91C_PWMC_IER) // (PWMC) PWMC Interrupt Enable Register

// ========== Register definition for UDP peripheral ==========

#define UDP_ISR       (*AT91C_UDP_ISR) // (UDP) Interrupt Status Register

#define UDP_IDR       (*AT91C_UDP_IDR) // (UDP) Interrupt Disable Register

#define UDP_GLBSTATE (*AT91C_UDP_GLBSTATE) // (UDP) Global State Register

#define UDP_FDR       (*AT91C_UDP_FDR) // (UDP) Endpoint FIFO Data Register

#define UDP_CSR       (*AT91C_UDP_CSR) // (UDP) Endpoint Control and Status Register

#define UDP_RSTEP    (*AT91C_UDP_RSTEP) // (UDP) Reset Endpoint Register

#define UDP_ICR       (*AT91C_UDP_ICR) // (UDP) Interrupt Clear Register

#define UDP_IMR       (*AT91C_UDP_IMR) // (UDP) Interrupt Mask Register

#define UDP_IER       (*AT91C_UDP_IER) // (UDP) Interrupt Enable Register

#define UDP_FADDR    (*AT91C_UDP_FADDR) // (UDP) Function Address Register

#define UDP_NUM       (*AT91C_UDP_NUM) // (UDP) Frame Number Register

/* Port Pins */

#define PA0       (1<<0)

#define PA1       (1<<1)

#define PA2       (1<<2)

#define PA3       (1<<3)

#define PA4       (1<<4)

#define PA5       (1<<5)

#define PA6       (1<<6)

#define PA7       (1<<7)

#define PA8       (1<<8)

#define PA9       (1<<9)

#define PA10       (1<<10)

#define PA11       (1<<11)

#define PA12       (1<<12)

#define PA13       (1<<13)

#define PA14       (1<<14)

#define PA15       (1<<15)

#define PA16       (1<<16)

#define PA17       (1<<17)

#define PA18       (1<<18)

#define PA19       (1<<19)

#define PA20       (1<<20)

#define PA21       (1<<21)

#define PA22       (1<<22)

#define PA23       (1<<23)

#define PA24       (1<<24)

#define PA25       (1<<25)

#define PA26       (1<<26)

#define PA27       (1<<27)

#define PA28       (1<<28)

#define PA29       (1<<29)

#define PA30       (1<<30)

#define PA31       (1<<31)

#endif

net2wo · 发表于 2005-12-12 13:23:40

Thanks!

rafd · 发表于 2005-12-15 14:58:45

源模式寄存器和源向量寄存器，每组都有32个怎么，S64。H文件中就一个AIC_SMR和一个AIC_SVR积存器

偏移寄存器名称访问类型复位值

0000 源模式寄存器0 AIC_SMR0 读/ 写0x0

0x04 源模式寄存器1 AIC_SMR1 读/ 写0x0

– – – – –

0x7C 源模式寄存器31 AIC_SMR31 读/ 写0x0

0x80 源向量寄存器0 AIC_SVR0 读/ 写0x0

0x84 源向量寄存器1 AIC_SVR1 读/ 写0x0

– – – – –

0xFC 源向量寄存器31 AIC_SVR31 读/ 写0x0

dot2000 · 发表于 2006-1-19 09:43:35

有必要吗？

如果你看不习惯，到时候看9200的东西也会不习惯的。

yaoweiliang · 发表于 2006-5-12 18:06:16

去www.micrium.com网站找啊

zuoyou · 发表于 2006-5-13 14:08:52

好好的，改甚么！

hotpower · 发表于 2006-5-14 10:12:39

哈哈...那时还是菜鸟~~~不过AT的头文件并不太完美~~~

reloaded · 发表于 2010-8-12 15:38:53

不小心看到，不知道这位曾经的某论坛名人，如今是否还在搞电子哇？四年了呢。。不对从他离开这里也就两年吧。

看过某程序X人的书，发现他们那个年代，上论坛讨论问题几乎是解决现实问题的唯一方案，（因为他们大部分人英文很垃圾的缘故，其实很多问题外国佬早解决过了）

也许这些人都已经脱离这种所谓的“电子开发”的岗位了吧，也许是好事？

那时候（四五年前）搞电子可以买的起房子，现在不拿个万八千就肯定不可能买到房子
真是操性，，，遍地是民工，都tmd是民工，待遇民工化，生活水平民工化，学历越来越高。。。。
没发现最近一两年论坛新的项目越来越少了么？
有人想过为什么了吗？

ARM菜鸟改造令人烦恼的头文件AT91SAM7S64.H

阿莫论坛20周年了！感谢大家的支持与爱护！！