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发表于 2013-9-25 20:53:29
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//******************************************************************************
// MSP430F20xx Demo - Timer_A, Ultra-Low Pwr UART 2400 Echo, 32kHz ACLK
//
// Description: Use Timer_A CCR0 hardware output modes and SCCI data latch
// to implement UART function @ 2400 baud. Software does not directly read and
// write to RX and TX pins, instead proper use of output modes and SCCI data
// latch are demonstrated. Use of these hardware features eliminates ISR
// latency effects as hardware insures that output and input bit latching and
// timing are perfectly synchronised with Timer_A regardless of other
// software activity. In the Mainloop the UART function readies the UART to
// receive one character and waits in LPM3 with all activity interrupt driven.
// After a character has been received, the UART receive function forces exit
// from LPM3 in the Mainloop which echo's back the received character.
// ACLK = TACLK = LFXT1 = 32768Hz, MCLK = SMCLK = default DCO
// //* An external watch crystal is required on XIN XOUT for ACLK *//
//
// MSP430F20xx
// -----------------
// /|\| XIN|-
// | | | 32kHz
// --|RST XOUT|-
// | |
// | CCI0B/TXD/P1.5|-------->
// | | 2400 8N1
// | CCI0A/RXD/P1.1|<--------
//
#define RXD 0x02 // RXD on P1.1
#define TXD 0x20 // TXD on P1.5
// Conditions for 2400 Baud SW UART, ACLK = 32768
#define Bitime_5 0x06 // ~ 0.5 bit length + small adjustment
#define Bitime 0x0E // 427us bit length ~ 2341 baud
volatile unsigned int RXTXData;
volatile unsigned char BitCnt;
void TX_Byte (void);
void RX_Ready (void);
// M. Buccini / L. Westlund
// Texas Instruments Inc.
// October 2005
// Built with CCE Version: 3.2.0 and IAR Embedded Workbench Version: 3.40A
//******************************************************************************
#include <msp430.h>
/* main.c */
#include <stdio.h>
#include "linkedlist.h"
void print_item(link p)
{
printf("%d\n", p->item);
}
int main (void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer
CCTL0 = OUT; // TXD Idle as Mark
TACTL = TASSEL_1 + MC_2; // ACLK, continuous mode
P1SEL = TXD + RXD; //
P1DIR = TXD; //
P1DIR |= 0x01; // Set P1.0 to output direction
//LPM3;
// Mainloop
for (;;)
{
P1OUT ^= 0x01; // LED Flash
RX_Ready(); // UART ready to RX one Byte
_BIS_SR(LPM3_bits + GIE); // Enter LPM3 w/ interr until char RXed
TX_Byte(); // TX Back RXed Byte Received
link p = make_node(10);
insert(p);
p = make_node(5);
insert(p);
p = make_node(90);
insert(p);
p = search(5);
delete(p);
free_node(p);
traverse(print_item);
destroy();
p = make_node(100);
push(p);
p = make_node(200);
push(p);
p = make_node(250);
push(p);
while (p = pop())
{
print_item(p);
free_node(p);
}
}
}
// Function Transmits Character from RXTXData Buffer
void TX_Byte (void)
{
unsigned char Tar = 0; // Warning[Pa082]: undefined behavior: the order of volatile accesses is undefined in this statement
unsigned char Ccr = 0; //
BitCnt = 0xA; // Load Bit counter, 8data + ST/SP
Tar = TAR;
Ccr = CCR0;
//while ( CCR0 != TAR ) // Prevent async capture
// CCR0 = TAR; // Current state of TA counter
while ( Ccr != Tar ) // Prevent async capture
CCR0 = TAR; // Current state of TA counter
CCR0 += Bitime; // Some time till first bit
RXTXData |= 0x100; // Add mark stop bit to RXTXData
RXTXData = RXTXData << 1; // Add space start bit
CCTL0 = CCIS0 + OUTMOD0 + CCIE; // TXD = mark = idle
while ( CCTL0 & CCIE ); // Wait for TX completion
}
// Function Readies UART to Receive Character into RXTXData Buffer
void RX_Ready (void)
{
BitCnt = 0x8; // Load Bit counter
CCTL0 = SCS + OUTMOD0 + CM1 + CAP + CCIE; // Sync, Neg Edge, Cap
}
// Timer A0 interrupt service routine
#pragma vector=TIMERA0_VECTOR
__interrupt void Timer_A (void)
{
CCR0 += Bitime; // Add Offset to CCR0
// TX
if (CCTL0 & CCIS0) // TX on CCI0B?
{
if ( BitCnt == 0)
CCTL0 &= ~ CCIE; // All bits TXed, disable interrupt
else
{
CCTL0 |= OUTMOD2; // TX Space
if (RXTXData & 0x01)
CCTL0 &= ~ OUTMOD2; // TX Mark
RXTXData = RXTXData >> 1;
BitCnt --;
}
}
// RX
else
{
if( CCTL0 & CAP ) // Capture mode = start bit edge
{
CCTL0 &= ~ CAP; // Switch from capture to compare mode
CCR0 += Bitime_5;
}
else
{
RXTXData = RXTXData >> 1;
if (CCTL0 & SCCI) // Get bit waiting in receive latch
RXTXData |= 0x80;
BitCnt --; // All bits RXed?
if ( BitCnt == 0)
//>>>>>>>>>> Decode of Received Byte Here <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
{
CCTL0 &= ~ CCIE; // All bits RXed, disable interrupt
_BIC_SR_IRQ(LPM3_bits); // Clear LPM3 bits from 0(SR)
}
//>>>>>>>>>> Decode of Received Byte Here <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
}
}
}
/*------------------------------------------------------------------------------
if ((0x10 & P1IN)) P1OUT |= 0x01; // if P1.4 set, set P1.0
else P1OUT &= ~0x01; // else reset
------------------------------------------------------------------------------*/
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