开贴记录SWD 脱机烧录器开发过程，请各路大神指教

abbott.yang · 发表于 2015-8-21 11:03:16

参考 CMISI_DAP,BlackMagic代码。
预备下周末结案，目前方案：
1：Host用STM32F427，跑RTEMS系统， IO口模拟SWD时序。
2：flash的操作函数，由Host通过SWD下载入target ram执行。（CMISI_DAP采用这种方式）
不知道jlink的flash操作是不是一样的原理。他要适用这么多芯片，那得有准备多少这样的小程序啊。。。
3：USB用的虚拟串口，用ST官方提供的驱动，上位机编程简单。tafget本身程序.bin文件由上位机通过虚拟串口传入。
此虚拟串口的波特率，奇偶，起停位设置均形同虚设。

目前状态：
SWD时序基本调试通过，读写target ID/reg已经正常，暂时未经过高强度测试。。
正在弄flash操作。

aozima · 发表于 2015-8-21 11:24:53

不这样写入个小程序，针对每个芯片，不还得再写另一套程序嘛。
CMSIS_DAP的至少可以通用MDK的，省了你很多事。

abbott.yang · 发表于 2015-8-21 13:23:49

aozima 发表于 2015-8-21 11:24
不这样写入个小程序，针对每个芯片，不还得再写另一套程序嘛。
CMSIS_DAP的至少可以通用MDK的，省了你很多 ...

担心通过SWD去擦除比较慢！！
通过SWD 控制target的flash寄存器达到同样的效果。。。暂时还在实验中，但也会存在针对不同芯片寄存器表不同的问题。
写入小程序的方法，别人已经实现，成功的概率目前来看比较大！

bitcoin2 · 发表于 2015-8-21 14:12:11

精神上支持你

hanshiruo · 发表于 2015-8-21 14:14:27

本帖最后由 hanshiruo 于 2015-8-21 14:16 编辑

...........

shangdawei · 发表于 2015-8-21 14:19:10

>>>IO口模拟SWD时序。
这个能否使用Timer驱动，速度或许能高些。

xwiron · 发表于 2015-8-21 14:23:44

搬条板凳坐等》》》

aozima · 发表于 2015-8-21 14:28:22

abbott.yang 发表于 2015-8-21 13:23
担心通过SWD去擦除比较慢！！
通过SWD 控制target的flash寄存器达到同样的效果。。。暂时还在实验中，但 ...

擦除FLASH都是毫秒甚至秒级，由FLASH本身决定，这和SWD有毛关系？不用SWD能变快？

hanshiruo · 发表于 2015-8-21 14:28:28

本帖最后由 hanshiruo 于 2015-8-21 14:39 编辑

有现成的SWD脱机下载器，已经卖出许多，稳定可靠

czdavid · 发表于 2015-8-21 14:33:31

abbott.yang 发表于 2015-8-21 13:23
担心通过SWD去擦除比较慢！！
通过SWD 控制target的flash寄存器达到同样的效果。。。暂时还在实验中，但 ...

SWD擦除与FLASH自身参数有关，与SWD速度无关。

shangdawei · 发表于 2015-8-21 14:37:11

czdavid 发表于 2015-8-21 14:33
SWD擦除与FLASH自身参数有关，与SWD速度无关。

通过 SWD 控制target的flash寄存器达到同样的效果和
通过SWD下载程序到内部RAM来控制target的flash寄存器
两者速度是否会有些区别？

snoopyzz · 发表于 2015-8-21 14:40:07

shangdawei 发表于 2015-8-21 14:37
通过 SWD 控制target的flash寄存器达到同样的效果和
通过SWD下载程序到内部RAM来控制target的flash寄存器 ...

区分在于你直接写FLASH的时候, 要等待FLASH完成才能传输新数据

RAM执行程序的话, 可以在RAM->FLASH的过程中接收SWD->RAM的新数据

czdavid · 发表于 2015-8-21 14:47:35

shangdawei 发表于 2015-8-21 14:37
通过 SWD 控制target的flash寄存器达到同样的效果和
通过SWD下载程序到内部RAM来控制target的flash寄存器 ...

最简单和直接的就是直接SWD挂AHB总线控制target的FLASH寄存器。
当然为了效率和稳定性最好通过RAM缓冲。
至于时间上，不考虑稳定和出错这个因素，直接操作FLASH寄存器速度也不慢。

shangdawei · 发表于 2015-8-21 14:55:39

Freescale OSBDM JM60仿真器OSBDM Development Port Interfaces

BGND Interface

The BGND interface provides the standard 6 pin connection for the single wire BGND signal type development port.

Target types that apply this development port are the 9S08, RS08, and Coldfire V1.

+V_TRG, TBGND, TRG_RST*, and Ground are applied by this port type.

The BGND interface applies U4 as the signal transceiver.

U4 is a 74LVC1T45 logic gate with voltage level shifting features.

Operation on the target side (+V_TRG) is 1.8V to 5.5V.

The JM60 side is always +5V from the +5V_SW signal.

JM60 signals TBGND_EN, TBGND_IN, and TBGND_OUT provide the communication and control for this interface.

All these signals are associated with JM60 timer channels for precise timing capability to a 41.67ns time step period.

For more information on the input and output ports, refer to the Signal Chart section.

TBGND_ EN provides directional control for transmit or receive operations.

The signal is logic high for transmit output and logic low to receive input.

JM60 timer 2 channel 1 provides the primary signal direction control during the communication with the target.

The idle condition is low so that the interface is not driven unless the communication is intended.

During the communication, the direction is fixed to output the command to the target.

During the reception, the signal is timed in edge aligned PWM mode to provide the BGND start pulse prior to the target reply input.

TBGND_OUT provides the transmit signal output from the JM60 to the target.

Timer 2 channel 0 controls this signal in edge aligned PWM mode.

For data transmission, the timer channel will output an active low signal with a time period that represents a logic one bit value or logic 0 bit value.

In receive mode, the timer channel will provide a low output for the start bit on the BGND signal and then provide timing internally for the reply signal input time window.

TBGND_IN provides receive signal input from the target to the JM60.

Timer 1 channel 3 is applied to measure the input signal duration in capture mode (25Mhz BDC clock maximum).

This operation provides the timing to determine a logic 1 or 0 bit value input from the target.

RS08 type targets apply a lower speed communication technique that inputs the JM60 port value (sample mode) instead of using the timer capture.

This is due to the RS08 will not provide a stable input signal after the start bit generation and creates false timer capture edges.

Other undefined target types may exhibit the same issue and may apply sample mode, if required (10MHz BDC clock maximum).

NOTE The TBGND_OUT and TBGND_IN signals are connected with resistor R1. R1 provides isolation between the 2 timer channels.

tang0571 · 发表于 2015-8-21 15:03:27

sw离线烧录，留名，有时间自己整一个，通用的离线烧录器局限性太多！

shangdawei · 发表于 2015-8-21 15:04:00

abbott.yang · 发表于 2015-8-21 16:12:32

shangdawei 发表于 2015-8-21 14:19
>>>IO口模拟SWD时序。
这个能否使用Timer驱动，速度或许能高些。

观察了SWD波形，想用SPI的8字节数据去套这个协议。。可惜都不是8字节对齐，中间还有有接收ACK。。。shangdawei 给的电路是要SPI的I/O接一起同时收发的意思？Out线上电阻不好挑，大了out线驱动力不足，小了IN线上target拉不低/高。还要配好数据发送，然后从回来的数据中挑出ACK以及数据，一样费CPU时间。不知道Jlink里面是怎么控制速度的。它的波形很好，JTAG转SWD，它正好是56个时钟，估计是用的SPI吧，有了解的么？
用Timer如果快起来的话，Timer中断会很频繁，看Jlink可以设置10M。。。timer中断间隔就要设置为1/20M，50ns。我是怕1us以下的中断系统难以承受。。
这个尝试后面再说。先把基本的弄起来再考虑速度优化！

abbott.yang · 发表于 2015-8-21 16:17:57

本帖最后由 abbott.yang 于 2015-8-21 16:19 编辑

shangdawei 发表于 2015-8-21 14:37
通过 SWD 控制target的flash寄存器达到同样的效果和
通过SWD下载程序到内部RAM来控制target的flash寄存器 ...

区别很小吧，特别是SWD速度够快的时候。blackmagic和DAP不同，它是用SWD直接操作target flash寄存器来完成的。
IO模拟速度慢，然后考虑的是做这个脱机烧录只是我要做的东西的一部分，后面会把整个产线的一些功能都集成进来，所以在启动时一次性把程序下进去完事。操作flash就可以少用几个SWD读写动作。
省点点时间，蚊子小也有肉。以前用资源，时钟很少很慢的低级MCU留下的习惯，比较抠门！

abbott.yang · 发表于 2015-8-21 16:23:36

czdavid 发表于 2015-8-21 14:47
最简单和直接的就是直接SWD挂AHB总线控制target的FLASH寄存器。
当然为了效率和稳定性最好通过RAM缓冲。
...

David童鞋你的东西做好了没。。。。
我还想向你请教来着。就是积分低啊，不能发消息不能加好友！
万恶的积分！！！！

shangdawei · 发表于 2015-8-21 18:55:01

落叶随风 · 发表于 2015-8-21 20:35:13

给自己公司做了一个SWD的烧写器，用的IO模拟，就是速度上不去

shangdawei · 发表于 2015-8-21 20:50:00

Programming Internal Flash Over the Serial Wire Debug Interface

This document explains how to access the debug interface of the EFM32 and how to use this interface to program devices (load applications into flash).
It also explains how to lock and unlock debug access to the MCU to protect the contents of the internal flash and SRAM.

shangdawei · 发表于 2015-8-21 20:57:49

Programming Internal Flash Over the Serial Wire Debug Interface

whatcanitbe · 发表于 2015-8-22 07:38:56

好样的，弄好了普及一下

shangdawei · 发表于 2015-8-22 09:50:44

abbott.yang 发表于 2015-8-21 16:12
观察了SWD波形，想用SPI的8字节数据去套这个协议。。可惜都不是8字节对齐，中间还有有接收ACK。。。shang ...

>> 正好是56个时钟 ?

拦截V9的波形，这个是51个时钟吧？

shangdawei · 发表于 2015-8-22 17:50:13

Programming internal SRAM over SWD

This documentation describe how to programming ARM Cortex M3 internal SRAM over SWD(Serial Wire Debug) interface. For this purpose, something we too know.

SWD communication protocol. We need to know Low level timing requirement, that is foundation to exchange command and data between debugger and target MCU.
Read/write data from/to internal SRAM. We need to know how to program firmware into desired address, like SRAM(0x20000000). That needs us to know SW-DAP registers usage. Pass address and data over those registers and then into internal SRAM.
Make code running from SRAM. We need to change vector table entry from internal flash to SRAM; And SP and PC also needed change to SRAM location. That need us to know the cortex M3 debug and system registers usage.
We choose Silabs SiM3U167 as target MCU in this implementation. We implement a high level protocol with python script, it calls Silabs provided DLL file interface to access Silabs USB Debug Adapter. Also, we provide a firmware running from C8051F380, it contains a full implementation on both low level communicating timing and high level programming SRAM protocol.

shangdawei · 发表于 2015-8-22 18:11:50

Serial Wire Debug (SWD) Open Library for low level Debug Access Port (DAP) on new ARM Cortex CPU devices.

This is an official website of the LibSWD Project - Free and Open solution for accessing the SW-DP (Serial Wire Debug Port)
on ARM-Cortex CPU based embedded systems. Source code is released under "new" 3 clause BSD License.

shangdawei · 发表于 2015-8-22 18:30:35

MBED-HDK SWD Interface

shangdawei · 发表于 2015-8-22 21:15:57

IBDAP-CMSIS-DAP IO模拟SWD时序

Armstart's CMSIS-DAP firmware implementation in gcc and makefile.

shangdawei · 发表于 2015-8-22 21:19:13

swddude -- A SWD programmer for ARM Cortex microcontrollers.

需要提供底层驱动

#ifndef SWD_H
#define SWD_H
/*
* Abstract base class for SWD interface drivers.
*/
#include "libs/error/error_stack.h"
#include <stdint.h>
/*
* SWDDriver provides a low-level interface to SWD interface devices.
* Each function maps directly to a SWD protocol concept. The ARM ADIv5
* specification explains the SWD protocol in more detail; it's available
* behind a clickwrap license on ARM's site.
*
* Client software should rarely interact with SWDDriver directly. Instead,
* wrap it in another object that provides a higher-level more pleasant
* interface with support for things like retries and named registers.
*/
class SWDDriver {
public:
/*
* Creates an instance of the driver. Because the constructor can't
* return any meaningful error condition, implementations should only do
* things that can't fail -- such as copying in constructor arguments
* and initializing memory.
*/
SWDDriver() {}
/*
* Destroys this driver instance. Because the destructor can't return
* any meaningful error condition, any resource cleanup here is
* last-resort. Clients should call the close() function to clean up
* resources in a way that can report errors. Destructor
* implementations may optionally log attempts to destroy a driver
* instance without calling close(), as this indicates a programming
* error.
*/
virtual ~SWDDriver() {}
/*
* Initialize the SWD link to the target, per the "Connection and line
* reset sequence" defined by the ARM ADI v5. This has two parts:
* 1. 50 clocks with the SWDIO line held high by the master.
* 2. A read of the IDCODE register in the DP.
*
* Because this function reads IDCODE behind the scenes, it can
* optionally return it to the application through the pointer argument.
*
* If this function returns successfully, it indicates that the
* interface is functioning, and that an attached microprocessor has
* responded to us. The state of the target is unknown -- in
* particular, the contents of the Debug Access Port's SELECT and
* CTRL/STAT registers are undefined.
*
* Return values:
* Err::success - initialization complete, target responded, IDCODE
* valid.
* Err::failure - initialization failed or target failed to respond.
*/
virtual Err::Error initialize(uint32_t * idcode_out = 0) = 0;
/*
* Asserts the target's reset line continuously until a call to
* leave_reset.
*
* Return values:
* Err::success - reset asserted.
* Err::failure - communications with interface failed.
*/
virtual Err::Error enter_reset() = 0;
/*
* Deasserts the target's reset line, allowing it to run.
*
* Return values:
* Err::success - reset deasserted.
* Err::failure - communications with interface failed.
*/
virtual Err::Error leave_reset() = 0;
/*
* Reads a 32-bit register from either the Debug Access Port (when
* debug_port is true) or the Access Port bank named in the DAP's SELECT
* register (when debug_port is false).
*
* Access Port reads are delayed: each read returns the result of the
* previous operation. To kick off a read without retrieving the
* results of the last one, pass a data pointer of zero; the result
* won't be written. To retrieve the results of the last Access Port
* read without starting a new one, read the Debug Access Port's RDBUFF
* register instead.
*
* Note that some registers can only be accessed in particular states of
* the CTRL/STAT register, and some registers can't be read at all.
*
* Refer to the ARM ADIv5 spec for more information.
*
* Implementation note: drivers should implement this function such that
* it will work regardless of mode. In particular, it must not assume
* that Overrun Detection is enabled in the DAP.
*
* Return values:
* Err::success - read completed, data valid.
* Err::try_again - target returned SWD WAIT response, read not
* completed.
* Err::failure - read failed, either in the interface or due to SWD
* FAULT.
*/
virtual Err::Error read(unsigned address,
bool debug_port,
uint32_t * data) = 0;
/*
* Writes a 32-bit value into a register in either the Debug Access Port
* (when debug_port is true) or the Access Port bank named in the DAP's
* SELECT register (when debug_port is false).
*
* Access Port writes may take time to complete. For a MEM-AP, monitor
* the status of the TrInProg (transaction in progress) bit of the
* Access Port's CSW register to detect when another write may be
* issued.
*
* Note that some registers can only be accessed in particular states of
* the CTRL/STAT register, and some registers can't be written at all.
*
* Refer to the ARM ADIv5 spec for more information.
*
* Implementation note: drivers should implement this function such that
* it will work regardless of mode. In particular, it must not assume
* that Overrun Detection is enabled in the DAP.
*
* Return values:
* Err::success - write completed.
* Err::try_again - target returned SWD WAIT response, write not
* completed.
* Err::failure - write failed, either in the interface or due to SWD
* FAULT.
*/
virtual Err::Error write(unsigned address,
bool debug_port,
uint32_t data) = 0;
};
#endif // SWD_H

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yick · 发表于 2015-8-22 21:19:54

关注一下，虽然用这个，但是却对其不了解

shangdawei · 发表于 2015-8-22 22:28:45

http://mbed.org/handbook/cmsis-dap-interface-firmware

https://github.com/mbedmicro/CMSIS-DAP

The CMSIS-DAP Interface Firmware provides:

USB Mass Storage Device for drag and drop programming of the target chip
USB Communications Device Class for Serial Communication with the target chip
USB HID CMSIS-DAP for debugging
USB bootloader for updating the interface firmware itself

shangdawei · 发表于 2015-8-22 22:30:23

ARM调试接口SWD(Serial Wire Debug) 协议分析
http://www.amobbs.com/thread-5498445-1-1.html
(出处: amoBBS 阿莫电子论坛)

shangdawei · 发表于 2015-8-22 22:32:23

shangdawei · 发表于 2015-8-22 23:33:30

这个使用了 SPI 接口，可以参考一下。

混合模式，传送 Request 和 Data 时用 SPI，传送 ACK 时用模拟的。

//=================================================================================
// ARM SWD Mode Port Bit masks
//
#if (HW_CAPABILITY&CAP_SWD_HW)
#ifndef DATA_PORT
#define DATA_PORT PTAD
#define DATA_PORT_DDR PTADD
#define DATA_PORT_PER PTAPE
#endif
// SWD data out pin
#define SWD_OUT PTAD_PTAD2
#define SWD_OUT_BIT (2) // Bit number!
#define SWD_OUT_MASK (1<<SWD_OUT_BIT)
#define SWD_OUT_PER PTAPE_PTAPE2
#define SWD_OUT_DDR PTADD_PTADD2
// SWD data out 3-state control
#define SWD_OUT_EN PTAD_PTAD4
#define SWD_OUT_EN_BIT (4) // Bit number!
#define SWD_OUT_EN_MASK (1<<SWD_OUT_EN_BIT)
#define SWD_OUT_EN_PER PTAPE_PTAPE4
#define SWD_OUT_EN_DDR PTADD_PTADD4
// Following assume pin already configured by SWD_LOW(),SWD_HIGH(),SWD_3STATE()
#define SWD_ENABLE_ASM BCLR SWD_OUT_EN_BIT,DATA_PORT
#define SWD_3STATE_ASM BSET SWD_OUT_EN_BIT,DATA_PORT
#define SWD_LOW_ASM BCLR SWD_OUT_BIT,DATA_PORT
#define SWD_HIGH_ASM BSET SWD_OUT_BIT,DATA_PORT
#define SWD_DISABLE_ASM BCLR SWD_OUT_EN_BIT,DATA_PORT_DDR
#define SWD_ENABLE_DRV_ASM BSET SWD_OUT_EN_BIT,DATA_PORT_DDR
// Following configure pin & driver
#define SWD_LOW() (SWD_OUT=0, SWD_OUT_DDR=1, SWD_OUT_EN=0, SWD_OUT_EN_DDR=1)
#define SWD_HIGH() (SWD_OUT=1, SWD_OUT_DDR=1, SWD_OUT_EN=0, SWD_OUT_EN_DDR=1)
#define SWD_3STATE() (SWD_OUT_EN=1, SWD_OUT_EN_DDR=1, SWD_OUT_DDR=1)
#define SWD_DISABLE() (SWD_OUT_EN=1, SWD_OUT_EN_DDR=0, SWD_OUT_DDR=0) // PUPs
// SWD data in pin
#define SWD_IN PTAD_PTAD0
#define SWD_IN_BIT (0) // Bit number!
#define SWD_IN_MASK (1<<SWD_IN_BIT)
#define SWD_IN_PER PTAPE_PTAPE0
#define SWD_IN_DDR PTADD_PTADD0
// SWCLK out pin
#define SWCLK_OUT PTAD_PTAD3
#define SWCLK_OUT_BIT (3) // Bit number!
#define SWCLK_OUT_MASK (1<<SWCLK_OUT_BIT)
#define SWCLK_OUT_PER PTAPE_PTAPE3
#define SWCLK_OUT_DDR PTADD_PTADD3
// SWCLK enable pin - controls buffer enable
#define SWCLK_OUT_EN PTBD_PTBD1
#define SWCLK_OUT_EN_BIT (1) // Bit number!
#define SWCLK_OUT_EN_MASK (1<<SWCLK_OUT_EN_BIT)
#define SWCLK_OUT_EN_PER PTBPE_PTBPE1
#define SWCLK_OUT_EN_DDR PTBDD_PTBDD1
// Following assume pin direction already set
#define SWCLK_LOW_ASM BCLR SWCLK_OUT_BIT,DATA_PORT
#define SWCLK_HIGH_ASM BSET SWCLK_OUT_BIT,DATA_PORT
// Following configure pin & driver
#define SWCLK_LOW() (SWCLK_OUT=0, SWCLK_OUT_DDR=1, SWCLK_OUT_EN=0, SWCLK_OUT_EN_DDR=1)
#define SWCLK_HIGH() (SWCLK_OUT=1, SWCLK_OUT_DDR=1, SWCLK_OUT_EN=0, SWCLK_OUT_EN_DDR=1)
#define SWCLK_3STATE() (SWCLK_OUT_EN=1, SWCLK_OUT_EN_DDR=1, SWCLK_OUT_DDR=1) // PUPs
#define SWCLK_DISABLE() (SWCLK_OUT_EN=1, SWCLK_OUT_EN_DDR=0, SWCLK_OUT_DDR=0) // PUPs
#endif // CAP_SWD

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/*
* SWD.h
*
* Created on: 04/08/2012
* Author: PODonoghue
*/
#ifndef SWD_H_
#define SWD_H_
#include "Common.h"
// Ack values displaced by offset introduced during read (left justified 8-bit value)
#define SWD_ACK_OK (0x1<<5)
#define SWD_ACK_WAIT (0x2<<5)
#define SWD_ACK_FAULT (0x4<<5)
#define SWD_ACK_PROTOCOL (0x7<<5)
void swd_interfaceIdle(void);
void swd_init(void);
void swd_txIdle8(void);
U8 swd_test(void);
U8 swd_sendCommandWithWait(U8 command);
U8 swd_connect(void);
U8 swd_readReg(U8 command, U8 *data);
U8 swd_writeReg(U8 command, const U8 *data);
U8 swd_readAPReg(const U8 *address, U8 *buff);
U8 swd_writeAPReg(const U8 *address, const U8 *buff);
U8 swd_clearStickyError(void);
U8 swd_abortAP(void);
#endif /* SWD_H_ */

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/*! \file
\brief ARM-SWD routines
\verbatim
USBDM
Copyright (C) 2007 Peter O'Donoghue
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
\endverbatim
Change History
+==================================================================================================
| 21 Feb 2014 | Fixed unbalanced stack in swd_sendCommandWithWait() V4.10.6.30
| 10 Feb 2014 | Dramatically extended retry times to allow for slow clocks V4.10.6.20
| 30 Aug 2012 | ARM-JTAG & ARM-SWD Changes V4.9.5
+==================================================================================================
\endverbatim
*/
#include "Common.h"
#include "Configure.h"
#include "Commands.h"
#include "SWD.h"
#include "Commands.h"
#include "BDM.h"
#include "BDM_CF.h"
#include "CmdProcessing.h"
#include "BDMCommon.h"
#include "SPI.h"
#include "TargetDefines.h"
#include "SWD.h"
#if TARGET_CAPABILITY & CAP_ARM_SWD
//! SPI Masks - Mask to enable SPI as master Tx
#define SPIxC1_OFF (SPIxC1_MSTR_MASK) //!< SPI Masks - Mask to disable SPI
#define SPIxC1_M_ON_TX (SPIxC1_SPE_MASK|SPIxC1_MSTR_MASK|SPIxC1_CPOL_MASK|SPIxC1_CPHA_MASK|SPIxC1_SSOE_MASK|SPIxC1_LSBFE_MASK)
#define SPIxC1_M_ON_RX (SPIxC1_SPE_MASK|SPIxC1_MSTR_MASK|SPIxC1_CPOL_MASK) //!< SPI Masks - Mask to enable SPI as master Tx
#define SPIxC2_M_8 (0) //!< SPI Masks - 8-bit mode
#define SPIxC2_M_16 (SPIxC2_SPIMODE_MASK) //!< SPI Masks - 8-bit mode
// Can't use enumerations in assembly code
#define BDM_RC_OKx (0)
#define BDM_RC_NO_CONNECTIONx (5)
#define BDM_RC_ACK_TIMEOUTx (30)
#define BDM_RC_ARM_PARITY_ERRORx (51)
#define BDM_RC_ARM_FAULT_ERRORx (52)
#define SWD_READ_IDCODE 0xA5 // (Park,Stop,Parity,A[32],R/W,AP/DP,Start) = 10100101
// Masks for SWD_WR_DP_ABORT clear sticky
#define SWD_DP_ABORT_CLEAR_STICKY_ERRORS_B3 0x1E
// Masks for SWD_WR_DP_ABORT abort AP
#define SWD_DP_ABORT_ABORT_AP_B3 0x01
// Masks for SWD_RD_DP_STATUS
#define SWD_RD_DP_STATUS_ANYERROR_B3 0xB2
#pragma MESSAGE DISABLE C1404 // Disable warnings about missing return value
#pragma MESSAGE DISABLE C5703 // Disable warnings about unused parameter
//! Sets the SWD interface to an idle state
//! RESET=3-state, SWCLK=High, SWDIO=3-state (SPI off)
//!
void swd_interfaceIdle(void) {
#ifdef RESET_3STATE
RESET_3STATE();
#endif
SWD_3STATE();
SWCLK_HIGH();
SPIC1 = SPIxC1_OFF;
}
//! Initialise the SWD interface and sets it to an idle state
//! RESET=3-state, SWCLK=High, SWDIO=3-state
//!
//! @note This includes once-off initialisation such as PUPs etc
//!
void swd_init(void) {
// 4 pins SWD_OUT, SWD_OUT_EN, SWCLK_OUT, SWCLK_OUT_EN
// Individually controlled PUPs
SWD_OUT_PER = 1; // Prevent float when disabled
SWD_OUT_EN_PER = 1; // Prevent drive when disabled
SWCLK_OUT_PER = 1; // Prevent float when disabled
SWCLK_OUT_EN_PER = 1; // Prevent drive when disabled
SWD_IN_DDR = 0; // Make input
SWD_IN_PER = 1; // Shouldn't be req. as external PUP for speed
#ifdef RESET_IN_DDR
RESET_IN_DDR = 0; // Make input
#endif
#ifdef RESET_IN_PER
RESET_IN_PER = 1; // Needed for input level translation to 5V
#endif
#ifdef RESET_OUT_PER
RESET_OUT_PER = 1; // Holds RESET_OUT inactive when unused
#endif
(void)spi_setSpeed(0);
swd_interfaceIdle();
}
//! Turns off the SWD interface
//!
//! Depending upon settings, may leave target power on.
//!
void swd_off( void ) {
#if ((HW_CAPABILITY & CAP_FLASH) != 0)
(void)bdmSetVpp(BDM_TARGET_VPP_OFF);
#endif
if (!bdm_option.leaveTargetPowered) {
VDD_OFF();
}
swd_interfaceIdle();
SWCLK_DISABLE();
SWD_DISABLE();
RESET_DISABLE();
}
#define SWD_DATA1_CLK1 SWCLK_OUT_MASK|SWD_OUT_EN_MASK
#define SWD_DATA0_CLK1 SWCLK_OUT_MASK|0
//! Transmits 1 clock with SWDIO 3-state
//!
void swd_turnAround() {
asm {
// 1 clock turn-around
mov #SWD_OUT_MASK,DATA_PORT // SWDIO=3-state,SWCLK=0
ldx bitDelay // Low time delay
dbnzx *-0 // [4n fppp]
bset SWCLK_OUT_BIT,DATA_PORT // SWCLK=1
ldx bitDelay // High time delay
dbnzx *-0 // [4n fppp]
}
}
//! Transmits 8-bits of idle (SDIO=0)
//!
void swd_txIdle8(void) {
asm {
mov #SPIxC2_M_8,SPIxC2 // Initialise SPI (8 bit)
mov #SPIxC1_M_ON_TX,SPIC1 // Enable SPI
clr DATA_PORT // Enable SWD drive
cmp SPIxS // Dummy status read
clr SPIxD // Tx data (=0)
L1:
brclr SPIS_SPRF_BIT,SPIxS,L1 // Wait until Tx/Rx complete
lda SPIxD // Discard rx data
mov #SWCLK_OUT_MASK|SWD_OUT_EN_MASK,DATA_PORT // Setup for SWCLK=1, SWD=3-state
clr SPIC1 // Disable SPI
}
}
#if (SWD_IN_BIT != 0)
#error "SWD_IN must be bit #0"
#endif
#pragma MESSAGE DISABLE C5703 // Disable warnings about unused parameter
//! SWD command phase
//!
//! Writes 8-bit command and receives 3-bit response
//! It will retry on WAIT response a limited number of times
//!
//! @param command - 8-bit command to write to SWD (including parity!)
//!
//! @return \n
//! == \ref BDM_RC_OK => Success \n
//! == \ref BDM_RC_ARM_FAULT_ERROR => FAULT response from target \n
//! == \ref BDM_RC_ACK_TIMEOUT => Excessive number of WAIT responses from target \n
//! == \ref BDM_RC_NO_CONNECTION => Unexpected/no response from target
//!
//! @note A turn-around clock period will be added on error responses
//!
uint8_t swd_sendCommandWithWait(uint8_t command) {
asm {
sta txTiming1 // Save data (for retry)
ldx #(2000/250) // Set up outer retry count
retry_outer:
pshx // Save outer retry count
mov #250,rxTiming1 // Reset inner retry count
retry:
// 8-bit Start|APnDP|R/W|Parity|Stop|Park
lda txTiming1 // Get Tx data
mov #SPIxC2_M_8,SPIxC2 // Initialise SPI (8 bit)
mov #SPIxC1_M_ON_TX,SPIC1 // Enable SPI
clr DATA_PORT // Enable SWD drive
cmp SPIxS // Dummy status read
sta SPIxD // Tx data
L1:
brclr SPIS_SPRF_BIT,SPIxS,L1 // Wait until Tx/Rx complete
ldx SPIxD // Discard rx data
SWD_3STATE_ASM // SWD=3-state
clr SPIC1 // Disable SPI
// 1 clock turn-around
bclr SWCLK_OUT_BIT,DATA_PORT // SWCLK=0
ldx bitDelay // Low time delay
dbnzx *-0 // [4n fppp]
bset SWCLK_OUT_BIT,DATA_PORT // SWCLK=1
ldx bitDelay // High time delay
dbnzx *-0 // [4n fppp]
// 1st bit ACK
clra // Clear initial data value
bclr SWCLK_OUT_BIT,DATA_PORT // SWCLK=0
ldx bitDelay // Low time delay
dbnzx *-0 // [4n fppp]
ldx DATA_PORT // Capture data before rising edge
rorx
rora
bset SWCLK_OUT_BIT,DATA_PORT // SWCLK=1
ldx bitDelay // High time delay
dbnzx *-0 // [4n fppp]
// 2nd bit ACK
bclr SWCLK_OUT_BIT,DATA_PORT // SWCLK=0
ldx bitDelay // Low time delay
dbnzx *-0 // [4n fppp]
ldx DATA_PORT // Capture data before rising edge
rorx
rora
bset SWCLK_OUT_BIT,DATA_PORT // SWCLK=1
ldx bitDelay // High time delay
dbnzx *-0 // [4n fppp]
// 3rd bit ACK
bclr SWCLK_OUT_BIT,DATA_PORT // SWCLK=0
ldx bitDelay // Low time delay
dbnzx *-0 // [4n fppp]
ldx DATA_PORT
rorx
rora
bset SWCLK_OUT_BIT,DATA_PORT // SWCLK=1
ldx bitDelay // High time delay
dbnzx *-0 // [4n fppp]
tax
lda #BDM_RC_OKx
cbeqx #SWD_ACK_OK,balanceStack
// Do turn-around clock on anything other than ACK_OK response
bclr SWCLK_OUT_BIT,DATA_PORT // SWCLK=0
lda bitDelay // Low time delay
dbnza *-0 // [4n fppp]
bset SWCLK_OUT_BIT,DATA_PORT // SWCLK=1
lda bitDelay // High time delay
dbnza *-0 // [4n fppp]
// Check for wait response
cpx #SWD_ACK_WAIT // Wait response?
bne identifyError // No - exit with other error
// Check for wait timeout
dbnz rxTiming1,retry // Retry limit reached
pulx
dbnzx retry_outer
lda #BDM_RC_ACK_TIMEOUTx // Too many retries
bra done // Return error (stack already balanced)
identifyError:
lda #BDM_RC_ARM_FAULT_ERRORx // Identify error
cbeqx #SWD_ACK_FAULT,balanceStack
lda #BDM_RC_NO_CONNECTIONx
balanceStack:
pulx // Balance stack
done:
}
}
#pragma MESSAGE DEFAULT C5703 // Restore warnings about unused parameter
#pragma MESSAGE DISABLE C5703 // Disable warnings about unused parameter
//! Transmits 32-bit value
//!
//! Sequence as follows:
//! - 1-clock turn-around
//! - 32-bit data value
//! - 1-bit parity
//! - 8-bit idle
//!
//! @param data - ptr to 32-bit data to Tx
//!
static void swd_tx32(const uint8_t *data) {
asm {
// 1 clock turn-around
bclr SWCLK_OUT_BIT,DATA_PORT // SWCLK=0
lda bitDelay // Low time delay
dbnza *-0 // [4n fppp]
bset SWCLK_OUT_BIT,DATA_PORT // SWCLK=1
mov #SPIxC2_M_16,SPIxC2 // Initialise SPI (16 bit)
mov #SPIxC1_M_ON_TX,SPIxC1 // Enable SPI
clr DATA_PORT // Enable SWD drive
cmp SPIxS // Dummy status read
lda 3,x // Start Tx 1st & 2nd bytes
sta SPIxDL
lda 2,x
sta SPIxDH
lda 0,x // Do byte-wide parity
eor 1,x
eor 2,x
eor 3,x
ldhx 0,x // Get 3rd & 4th bytes
L1:
brclr SPIS_SPRF_BIT,SPIxS,L1 // Wait until previous Tx/Rx complete
cphx SPIxD16 // Discard read data
sthx SPIxD16 // Tx 3rd & 4th bytes
// Calculate nibble parity
psha // [2]
nsa // [1]
eor 1,sp // [4]
ais #1 // [2]
// Calculate final parity
tax // [1]
clra // [1]
rorx // [1]
adc #0 // [2]
rorx // [1]
adc #0 // [2]
rorx // [1]
adc #0 // [2]
rorx // [1]
adc #0 // [2]
//parity in A.0
L2:
brclr SPIS_SPRF_BIT,SPIxS,L2 // Wait until previous Tx/Rx complete
ldhx SPIxD16 // Discard read data
#if SWD_OUT_BIT >= 1 // move to SWD_OUT position
lsla
#endif
#if SWD_OUT_BIT == 2
lsla
#else
#error Fix this code
#endif
and #SWD_OUT_MASK // SWD=p, SWCLK=0
sta DATA_PORT // Set up - no effect yet
ldx bitDelay // Low time delay
clr SPIC1 // Disable SPI,
dbnzx *-0 // [4n fppp]
bset SWCLK_OUT_BIT,DATA_PORT // SWD=p, SWCLK=1
// Start Tx of 8-bit idle
mov #SPIxC2_M_8,SPIxC2 // Initialise SPI (8 bit)
mov #SPIxC1_M_ON_TX,SPIC1 // Enable SPI
clr DATA_PORT // Enable SWD drive
cmp SPIxS // Dummy status read
clr SPIxD // Tx data (=0)
// Wait for Idle Tx to complete
L3:
brclr SPIS_SPRF_BIT,SPIxS,L3 // Wait until Tx/Rx complete
cmp SPIxD // Discard rx data
mov #SWCLK_OUT_MASK|SWD_OUT_EN_MASK,DATA_PORT // Setup for SWCLK=1, SWD=3-state
clr SPIC1 // Disable SPI
rts
}
}
#pragma MESSAGE DEFAULT C5703 // Restore warnings about unused parameter
#pragma MESSAGE DISABLE C5703 // Disable warnings about unused parameter
//! Receives a 32-bit value with parity at end (33 total)
//!
//! Sequence as follows:
//! - 32-bit data value
//! - 1-bit parity
//! - 8-bit idle
//!
//! @param data - ptr to buffer for Rx data
//!
//! @return BDM_RC_OK \n
//! BDM_RC_ARM_PARITY_ERROR
//!
static uint8_t swd_rx32(uint8_t *data) {
#define SPIS_SPTEF_BIT (5)
#define SPIS_SPRF_BIT (7)
asm {
SWD_3STATE_ASM // SWD=3-state
mov #SPIxC2_M_16,SPIxC2 // Initialise SPI (16 bit)
mov #SPIxC1_M_ON_TX,SPIxC1 // Enable SPI
cmp SPIxS // Dummy status read
sthx SPIxD16 // Tx dummy/Rx
L1:
brclr SPIS_SPRF_BIT,SPIxS,L1 // Wait until Rx complete
lda SPIxDH // Save data
sta 2,x
lda SPIxDL
sta 3,x
sthx SPIxD16 // Tx dummy/Rx
L2:
brclr SPIS_SPRF_BIT,SPIxS,L2 // Wait until Rx complete
lda SPIxDH // Save data
sta 0,x
lda SPIxDL
sta 1,x
bclr SWCLK_OUT_BIT,DATA_PORT // Setup for SWCLK=0
clr SPIC1 // Disable SPI (SWCLK=0)
// Parity bit
lda bitDelay // Low time delay
dbnza *-0 // [4n fppp]
lda DATA_PORT // Capture data before rising clock edge
bset SWCLK_OUT_BIT,DATA_PORT // SWCLK=1
and #SWD_IN_MASK // Convert parity to byte width
// Single Parity bit remains - position is unimportant
// Start Tx of 8-bit idle
mov #SPIxC2_M_8,SPIxC2 // Initialise SPI (8 bit)
mov #SPIxC1_M_ON_TX,SPIC1 // Enable SPI
clr DATA_PORT // Enable SWD drive
cmp SPIxS // Dummy status read
clr SPIxD // Tx data (=0)
// Do parity calculation
eor 0,x // Do byte-wide parity on data & parity bit
eor 1,x
eor 2,x
eor 3,x
ldx bitDelay // High time delay
dbnzx *-0 // [4n fppp]
// Calculate nibble parity
psha // [2]
nsa // [1]
eor 1,sp // [4]
ais #1 // [2]
// Calculate final parity
tax // [1]
clra // [1]
rorx // [1]
adc #0 // [2]
rorx // [1]
adc #0 // [2]
rorx // [1]
adc #0 // [2]
rorx // [1]
adc #0 // [2]
and #1
// Parity in A.0 - should be 0
beq okExit
lda #BDM_RC_ARM_PARITY_ERRORx
okExit:
// Wait for Idle Tx to complete
L3:
brclr SPIS_SPRF_BIT,SPIxS,L3 // Wait until Tx/Rx complete
cmp SPIxD // Discard rx data
mov #SWCLK_OUT_MASK|SWD_OUT_EN_MASK,DATA_PORT // Setup for SWCLK=1, SWD=3-state
clr SPIC1 // Disable SPI
rts
}
}
#pragma MESSAGE DEFAULT C5703 // Restore warnings about unused parameter
#pragma MESSAGE DISABLE C5703 // Disable warnings about unused parameter
//! Switches interface to SWD
//!
//! Sequence as follows:
//! - 64-bit sequence of 1's
//! - 8-bit magic number 0xE79E
//! - 64-bit sequence of 1's
//!
//! @note Interface is reset even if already in SWD mode so IDCODE must be read
//! to enable interface
//!
static void swd_JTAGtoSWD(void) {
asm {
mov #SPIxC2_M_16,SPIxC2 // Initialise SPI (16 bit)
mov #SPIxC1_M_ON_TX,SPIxC1 // Enable SPI
clr DATA_PORT // Enable SWD drive
cmp SPIxS // Dummy status read
bsr txOnes // Send 64 clocks
ldhx #0xE79E // Send magic #
sthx SPIxD16
L5:
brclr SPIS_SPTEF_BIT,SPIxS,L5 // Wait until Tx buffer empty
bsr txOnes // Send 64 clocks
L6:
brclr SPIS_SPTEF_BIT,SPIxS,L6 // Wait until Tx buffer empty
ldhx SPIxD16 // Discard last data
mov #SWCLK_OUT_MASK|SWD_OUT_EN_MASK,DATA_PORT // Setup for SWCLK=1, SWD=3-state
L7:
brclr SPIS_SPRF_BIT,SPIxS,L7 // Wait until Tx complete
ldhx SPIxD16 // Discard rx data
clr SPIC1 // Disable SPI (SWCLK=1)
rts
txOnes:
ldhx #0xFFFF // Tx 64 bits with '1'
sthx SPIxD16
L1:
brclr SPIS_SPTEF_BIT,SPIxS,L1 // Wait until Tx buffer empty
sthx SPIxD16
L2:
brclr SPIS_SPTEF_BIT,SPIxS,L2 // Wait until Tx buffer empty
sthx SPIxD16
L3:
brclr SPIS_SPTEF_BIT,SPIxS,L3 // Wait until Tx buffer empty
sthx SPIxD16
L4:
brclr SPIS_SPTEF_BIT,SPIxS,L4 // Wait until Tx buffer empty
rts
}
}
#pragma MESSAGE DEFAULT C5703 // Restore warnings about unused parameter
//! SWD - Try to connect to the target
//!
//! This will do the following:
//! - Switch the interface to SWD mode
//! - Read IDCODE
//!
//! @return \n
//! == \ref BDM_RC_OK => Success \n
//! == \ref BDM_RC_NO_CONNECTION => Unexpected/no response from target
//!
uint8_t swd_connect(void) {
uint8_t buff[4];
swd_JTAGtoSWD();
swd_txIdle8();
// Target must respond to read IDCODE immediately
return swd_readReg(SWD_READ_IDCODE, buff);
}
//! Read ARM-SWD DP & AP register
//!
//! @param command - SWD command byte to select register etc.
//! @param data - buffer for 32-bit value read
//!
//! @return \n
//! == \ref BDM_RC_OK => Success \n
//! == \ref BDM_RC_ARM_FAULT_ERROR => FAULT response from target \n
//! == \ref BDM_RC_ACK_TIMEOUT => Excessive number of WAIT responses from target \n
//! == \ref BDM_RC_NO_CONNECTION => Unexpected/no response from target \n
//! == \ref BDM_RC_ARM_PARITY_ERROR => Parity error on data read
//!
//! @note Action and Data returned depends on register (some responses are pipelined)\n
//! SWD_RD_DP_IDCODE - Value from IDCODE reg \n
//! SWD_RD_DP_STATUS - Value from STATUS reg \n
//! SWD_RD_DP_RESEND - LAST value read (AP read or DP-RDBUFF), FAULT on sticky error \n
//! SWD_RD_DP_RDBUFF - Value from last AP read and clear READOK flag in STRL/STAT, FAULT on sticky error \n
//! SWD_RD_AP_REGx - Value from last AP read, clear READOK flag in STRL/STAT and INITIATE next AP read, FAULT on sticky error
//!
uint8_t swd_readReg(uint8_t command, uint8_t *data) {
uint8_t rc = swd_sendCommandWithWait(command);
if (rc != BDM_RC_OK) {
return rc;
}
return swd_rx32(data);
}
//! Write ARM-SWD DP & AP register
//!
//! @param command - SWD command byte to select register etc.
//! @param data - buffer containing 32-bit value to write
//!
//! @return \n
//! == \ref BDM_RC_OK => Success \n
//! == \ref BDM_RC_ARM_FAULT_ERROR => FAULT response from target \n
//! == \ref BDM_RC_ACK_TIMEOUT => Excessive number of WAIT responses from target \n
//! == \ref BDM_RC_NO_CONNECTION => Unexpected/no response from target
//!
//! @note Action depends on register (some responses are pipelined)\n
//! SWD_WR_DP_ABORT - Write value to ABORT register (accepted) \n
//! SWD_WR_DP_CONTROL - Write value to CONTROL register (may be pending), FAULT on sticky error. \n
//! SWD_WR_DP_SELECT - Write value to SELECT register (may be pending), FAULT on sticky error. \n
//! SWD_WR_AP_REGx - Write to AP register. May initiate action e.g. memory access. Result is pending, FAULT on sticky error.
//!
uint8_t swd_writeReg(uint8_t command, const uint8_t *data) {
uint8_t rc = swd_sendCommandWithWait(command);
if (rc != BDM_RC_OK) {
return rc;
}
swd_tx32(data);
return rc;
}
//! Write register of Access Port
//!
//! @param 16-bit address \n
//! A[15:8] => DP-AP-SELECT[31:24] (AP # Select) \n
//! A[7:4] => DP-AP-SELECT[7:4] (Bank select within AP) \n
//! A[3:2] => APACC[3:2] (Register select within bank)
//! @param buff \n
//! - [1..4] => 32-bit register value
//!
//! @return
//! == \ref BDM_RC_OK => success
//!
//! @note - Access is completed before return
//!
uint8_t swd_writeAPReg(const uint8_t *address, const uint8_t *buff) {
static const uint8_t writeAP[] = {SWD_WR_AP_REG0, SWD_WR_AP_REG1, SWD_WR_AP_REG2, SWD_WR_AP_REG3};
uint8_t rc;
uint8_t regNo = writeAP[(address[1]&0xC)>>2];
uint8_t selectData[4];
selectData[0] = address[0];
selectData[1] = 0;
selectData[2] = 0;
selectData[3] = address[1]&0xF0;
// Set up SELECT register for AP access
rc = swd_writeReg(SWD_WR_DP_SELECT, selectData);
if (rc != BDM_RC_OK) {
return rc;
}
// Initiate write to AP register
rc = swd_writeReg(regNo, buff);
if (rc != BDM_RC_OK) {
return rc;
}
// Read from READBUFF register to allow stall/status response
return swd_readReg(SWD_RD_DP_RDBUFF, selectData);
}
//! Read register of Access Port
//!
//! @param 16-bit address \n
//! A[15:8] => DP-AP-SELECT[31:24] (AP # Select) \n
//! A[7:4] => DP-AP-SELECT[7:4] (Bank select within AP) \n
//! A[3:2] => APACC[3:2] (Register select within bank)
//! @param buff \n
//! - [1..4] => 32-bit register value
//!
//! @return
//! == \ref BDM_RC_OK => success
//!
//! @note - Access is completed before return
//!
uint8_t swd_readAPReg(const uint8_t *address, uint8_t *buff) {
static const uint8_t readAP[] = {SWD_RD_AP_REG0, SWD_RD_AP_REG1, SWD_RD_AP_REG2, SWD_RD_AP_REG3};
uint8_t rc;
uint8_t regNo = readAP[(address[1]&0xC)>>2];
uint8_t selectData[4];
selectData[0] = address[0];
selectData[1] = 0;
selectData[2] = 0;
selectData[3] = address[1]&0xF0;
// Set up SELECT register for AP access
rc = swd_writeReg(SWD_WR_DP_SELECT, selectData);
if (rc != BDM_RC_OK) {
return rc;
}
// Initiate read from AP register (dummy data)
rc = swd_readReg(regNo, buff);
if (rc != BDM_RC_OK) {
return rc;
}
// Read from READBUFF register
return swd_readReg(SWD_RD_DP_RDBUFF, buff);
}
//! ARM-SWD - clear sticky bits
//!
//! @return error code
//!
uint8_t swd_clearStickyError(void) {
static const uint8_t swdClearErrors[4] = {0,0,0,SWD_DP_ABORT_CLEAR_STICKY_ERRORS_B3};
return swd_writeReg(SWD_WR_DP_ABORT, swdClearErrors);
}
//! ARM-SWD - clear sticky bits and abort AP transactions
//!
//! @return error code
//!
uint8_t swd_abortAP(void) {
static const uint8_t swdClearErrors[4] =
{0,0,0,SWD_DP_ABORT_CLEAR_STICKY_ERRORS_B3|SWD_DP_ABORT_ABORT_AP_B3};
return swd_writeReg(SWD_WR_DP_ABORT, swdClearErrors);
}
uint8_t swd_test(void) {
return swd_connect();
// swd_JTAGtoSWD();
// return BDM_RC_OK;
// return swd_connect();
}
#endif // HW_CAPABILITY && CAP_SWD_HW

复制代码

shangdawei · 发表于 2015-8-25 16:19:31

abbott.yang 发表于 2015-8-21 16:12
观察了SWD波形，想用SPI的8字节数据去套这个协议。。可惜都不是8字节对齐，中间还有有接收ACK。。。shang ...

JLink 大概用到了 TIMER + SPI + DMA，没有频繁的中断。

huangqi412 · 发表于 2015-8-25 21:04:04

如果不是非要脱电脑用应该还是jlink dll加界面最省事通用

huangqi412 · 发表于 2015-8-25 21:06:57

abbott.yang 发表于 2015-8-21 16:12
观察了SWD波形，想用SPI的8字节数据去套这个协议。。可惜都不是8字节对齐，中间还有有接收ACK。。。shang ...

不知道jlink是怎么做的能到10m

HYLG · 发表于 2015-8-26 01:05:36

都支持些什么芯片呀。

xgzn · 发表于 2015-8-26 07:55:21

支持，开发新产品成长才会快

hxhz123456 · 发表于 2015-8-26 13:43:17

支持，这个可以学习学习的。

shangdawei · 发表于 2015-8-28 18:07:26

目前进度如何？是否打算开源呢？

半仙 · 发表于 2015-8-28 18:39:01

最近正好有需求，持续关注楼主进展

abbott.yang · 发表于 2015-8-28 19:54:48

shangdawei 发表于 2015-8-22 09:50
>> 正好是56个时钟 ?

我用的V8，用jflash，点connect的时候，是56个时钟！
项目目前还是一周前差不多。我在外面，其他的同事在做其他功能部分。
让大家失望了。。。。。。。。

shangdawei · 发表于 2015-8-28 20:17:13

abbott.yang 发表于 2015-8-28 19:54
我用的V8，用jflash，点connect的时候，是56个时钟！
项目目前还是一周前差不多。我在外面，其他的同事在 ...

看来V9和V8的实现方法是不一样的。

shangdawei · 发表于 2015-8-28 20:19:30

本帖最后由 shangdawei 于 2015-8-28 21:27 编辑

KT-link Interface

shangdawei · 发表于 2015-8-30 09:51:06

LPC-Link2_v3_Rev_A1

hanshiruo · 发表于 2015-8-31 12:25:33

半仙发表于 2015-8-28 18:39
最近正好有需求，持续关注楼主进展

我有SWD脱机下载器成品，如果需要可以联系我

abbott.yang · 发表于 2015-9-2 19:37:28

shangdawei 发表于 2015-8-28 18:07
目前进度如何？是否打算开源呢？

读各种ID，寄存器，读写RAM，读Flash都没问题了。
写Flash还是写不进去。。。虽然SWD给出的ACK是正确的，但是写完再读出来还是写之前的，擦除再写也一样，在查原因，写动作没有任何作用，尝试是否和flash锁定有关系。
寄存器有的写不进去，xpr，pc，lr写不进去。也是swd提示ACK_OK，读出来还是和写进去之前一样，原因待查。
等做完，确认各种动作都正常就开源吧，不过因为职业原因，只会给出SWD的操作函数源代码。这其实没多大意义，参考CMSIS—DAP和ARM以及CortexM3文档，应该难度不大的。
要的发消息给我吧，留下信箱，我还是新手上路，消息，加好友都不行，杯具了！！！

shangdawei · 发表于 2015-9-2 20:09:34

abbott.yang 发表于 2015-9-2 19:37
读各种ID，寄存器，读写RAM，读Flash都没问题了。
写Flash还是写不进去。。。虽然SWD给出的ACK是正确的， ...

论坛元老也加不了好友的。。。

xingjianpeng · 发表于 2015-9-3 15:20:03

观望制作记录。

shangdawei · 发表于 2015-9-4 20:48:05

ARM® DSTREAM™ System and Interface Design Reference

czdavid · 发表于 2015-9-5 13:31:37

abbott.yang 发表于 2015-9-2 19:37
读各种ID，寄存器，读写RAM，读Flash都没问题了。
写Flash还是写不进去。。。虽然SWD给出的ACK是正确的， ...

先擦除，然后读出来是不是已经擦除了。
写FLASH的时候要注意FLASH延迟。
我当时测STM32F030的时候FLASH的传输方式未用Packet模式，STM32F103是用的Packet模式。
迫于生计，以前做的离线下载器搞好了就给生产用了，并没花太多时间再继续深入研究，也只是搞了点皮毛，希望对你能有帮助。

abbott.yang · 发表于 2015-9-5 17:04:43

czdavid 发表于 2015-9-5 13:31
先擦除，然后读出来是不是已经擦除了。
写FLASH的时候要注意FLASH延迟。
我当时测STM32F030的时候FLASH的 ...

这个是我自己疏忽，没有unclok flash所致。写几个pc。xpr等写不进去也是犯低级错误。往里写了奇数。。。
然后。。。flash操作函数是直接拷贝的stm32库函数。
只是把寄存器读写全换成swd读写。这样效率很低。当然擦除flash可以直接用swd操作，没啥影响。但是大数据编程的时候，时间都浪费在swd 波形传输上了，还是直接download程序到ram执行最快。
大家可以看看Keil，它也是download程序到ram去弄的，在keil程序目录下，有个flash文件夹，里面就是每个芯片都有一段flash操作程序。

huangqi412 · 发表于 2015-9-5 21:43:56

abbott.yang 发表于 2015-9-5 17:04
这个是我自己疏忽，没有unclok flash所致。写几个pc。xpr等写不进去也是犯低级错误。往里写了奇数。。。
...

如果不是非要脱机不可不如用jlink做个上位机通用简单

shangdawei · 发表于 2015-9-5 22:12:37

abbott.yang 发表于 2015-9-5 17:04
这个是我自己疏忽，没有unclok flash所致。写几个pc。xpr等写不进去也是犯低级错误。往里写了奇数。。。
...

这样可以直接参考KEIL的算法吧。

abbott.yang · 发表于 2015-9-7 14:36:18

程序在内部ram中运行的速度，只有在内部flash内运行的一半左右。。

talkingbeast · 发表于 2015-9-7 16:03:30

此类需求好像已经有现成产品卖了。

hxhz123456 · 发表于 2015-9-16 14:37:23

不知道能不能一带多的脱机升级方案，不写bootloader的情况下。

magicoctoier1 · 发表于 2015-9-17 09:34:44

收藏下!

wofei3344 · 发表于 2015-10-28 20:06:48

Mark，留名~

chestert · 发表于 2015-10-28 22:21:53

火前留名

PaulDE · 发表于 2015-11-16 23:15:09

看得出来 shangdawei 收集研究了不少资料

tgwfcc · 发表于 2015-12-6 23:11:26

楼主，你好，我也在研究SWD的协议，现在读DP-ID和AP-ID已经可以了，读写目标板的普通寄存器时，只有几个寄存器可以读，其他的读取时的ack不正确，能不能请教下，QQ853678594，谢谢~

happyliu · 发表于 2016-2-5 14:15:27

看来通过swd个性定制的下载升级器还是有需求的，可以做成加密下载升级后自宫，还有就是生产上的bootload批量下载。也在研究中，想做个专用的bootload脱机下载器，

happyliu · 发表于 2016-2-12 19:00:45

基本成功，用的JLink ARM-OB硬件通过swd直接控制FALSH寄存器操作，目标板也是stm32f103c8,没有做速度上的优化，用IO口模拟操作，全部写完后再校验的话，速度比用J-FLASH慢一半左右，只烧写不校验的话速度与J-FLASH基本一样，还没法擦除写保护后下载，还在研究中。想做个下载个小时程序到RAM中运行烧写的，有时间再研究下。这个帖子中shangdawei给的资料帮助不小，参考后做的。里边代码不少可以直接修改过来用。

xyz543 · 发表于 2016-2-13 15:51:40

abbott.yang 发表于 2015-9-2 19:37
读各种ID，寄存器，读写RAM，读Flash都没问题了。
写Flash还是写不进去。。。虽然SWD给出的ACK是正确的， ...

告知楼主在此坛加好友的方法，楼主您用您于此坛的 ID 登入后再购买一个新的 ID 号，这新的 ID 号已默认就是与您是已加好友的了。
当然，楼主您也可以取消此好友的连接关系！

wofei3344 · 发表于 2016-2-14 21:10:08

tang0571 发表于 2015-8-21 15:03
sw离线烧录，留名，有时间自己整一个，通用的离线烧录器局限性太多！

确实是这样，我也期望能根据公司的需求DIY一个专属的，不需要支持那么多器件，只要能满足自己需求的就是最好的！！！

sklli · 发表于 2016-3-3 13:56:39

LZ，能给个完整的工程吗？现在正在弄SWD烧写器

mega1702 · 发表于 2016-3-3 17:12:27

收藏下!!!

tgwfcc · 发表于 2016-3-29 17:58:41

本帖最后由 tgwfcc 于 2016-3-29 18:03 编辑

happyliu 发表于 2016-2-12 19:00
基本成功，用的JLink ARM-OB硬件通过swd直接控制FALSH寄存器操作，目标板也是stm32f103c8,没有做速度上的优 ...

你好，请教下，我现在能读写FLASH控制寄存器，但是往FLASH某一个地址写数据的时候，ACK出错，这个是什么原因呢？
比如往0x08070000 写一个字节0x11，写完后，读0x08070000，ACK出错。
谢谢

deepway · 发表于 2016-3-29 18:11:00

学习了，mark一下

lqs123 · 发表于 2016-3-29 18:12:58

学习了一下脱机下载,mark

蓝蓝的恋 · 发表于 2016-5-20 14:28:09

这里好复杂，学习一下

Free_man · 发表于 2016-6-20 10:37:22

czdavid 发表于 2015-9-5 13:31
先擦除，然后读出来是不是已经擦除了。
写FLASH的时候要注意FLASH延迟。
我当时测STM32F030的时候FLASH的 ...

stm32 swd离线下载，到了控制寄存器编程到flash那里不懂怎么搞，可以指导一下吗？

sklli · 发表于 2016-8-8 16:46:51

好东西，资料很全

helislayer · 发表于 2016-8-8 17:34:59

Free_man 发表于 2016-6-20 10:37
stm32 swd离线下载，到了控制寄存器编程到flash那里不懂怎么搞，可以指导一下吗？ ...

这个最简单就是直接操作 flash 寄存器，flash 的速度我自己的比较是
比用程序来刷慢 1 倍左右所以也没有差很多。我用的 swd 速度是 3M
左右。

flash 寄存器操作 ACK 经常有 wait 出现要正确处理。

你直接操作 flash 寄存器成功以后再考虑用程序加载。
程序那个调试建议些个单布调试打印每一步的寄存器内容，
包括将要执行的指令。

然后你就可以从调试记录里面看出来你加载的程序哪
一步出问题了。

Free_man · 发表于 2016-8-10 10:36:43

helislayer 发表于 2016-8-8 17:34
这个最简单就是直接操作 flash 寄存器，flash 的速度我自己的比较是
比用程序来刷慢 1 倍左右所以也没有 ...

好的，谢谢！

zhangyh89 · 发表于 2016-11-3 18:39:50

我现在可以用swd直接操作flash的寄存器进行擦出操作，但擦除后怎么给写数据啊，我用swd在相应的地址写数据后，读FLASH_SR寄存器发现一只处于BUSY状态。之前写flash用的固件库，里面擦出页后，半字半字的写，不知到SWD里怎么写呀

君达 · 发表于 2016-11-5 23:08:04

太帅了，这种做法我觉得比较好，什么时候分享出来看看

jerry_chao · 发表于 2017-4-13 19:35:56

模拟SWD, JTAG ，太好了，谢谢

wsammy880 · 发表于 2017-8-4 20:42:28

good job

raywongm78 · 发表于 2017-8-4 21:49:05

学习了，mark一下

jinchenaquarius · 发表于 2017-8-7 12:02:54

正在学习做这个，顶一个

aduecho · 发表于 2017-8-10 14:58:54

jinchenaquarius 发表于 2017-8-7 12:02
正在学习做这个，顶一个

你的进度怎样了呢？这几天也在看，云里雾里...

霸气侧漏 · 发表于 2017-8-10 15:05:52

我搞定了，嘿嘿

jinchenaquarius · 发表于 2017-8-10 15:54:00

霸气侧漏发表于 2017-8-10 15:05
我搞定了，嘿嘿

能分享一下经验吗？

jinchenaquarius · 发表于 2017-8-10 15:55:08

aduecho 发表于 2017-8-10 14:58
你的进度怎样了呢？这几天也在看，云里雾里...

不是很好搞，先从模拟io做起吧，在转到硬件SPI上

小山有树 · 发表于 2017-10-19 18:29:54

你好，请问进展怎么样了，能否发我一份SWD的操作文件，pjf102@163.com 谢谢

hanqimin · 发表于 2017-12-19 13:20:53

。。。。。。。

gyd0317 · 发表于 2018-6-3 13:32:52

像STM32在指定的地址写入要编程的半字（2字节）,但是DAP操作好像都要4字节，不知道那部分写flash是怎么操作的

Dragontan · 发表于 2018-6-7 10:10:24

楼主的做出来了吗？

cloudboy · 发表于 2018-9-14 21:19:02

收藏收藏，日后看看

huangqi412 · 发表于 2018-9-15 11:37:29

gyd0317 发表于 2018-6-3 13:32
像STM32在指定的地址写入要编程的半字（2字节）,但是DAP操作好像都要4字节，不知道那部分写flash是怎么操作 ...

可以设置宽度

xuqianfeg321 · 发表于 2019-11-8 01:24:31

666666666666666666666666666666666666

songguoliang · 发表于 2021-7-13 11:10:30

为什么我读的ID始终不对

songguoliang · 发表于 2021-7-13 13:55:24

为什么我的ID读出来始终不对

霸气侧漏 · 发表于 2021-7-13 21:18:00

songguoliang 发表于 2021-7-13 13:55
为什么我的ID读出来始终不对

你猜

开贴记录SWD 脱机烧录器开发过程，请各路大神指教

阿莫论坛20周年了！感谢大家的支持与爱护！！

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