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发表于 2020-1-5 14:10:28
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既然决定作为毕业设计应该自己认真研究才对，
我提供几个思路给你：
首先应该了解原装USB-BLASTER的结构。 FT245+CPLD，
FT245主要实现了USB转并口的协议， STM32需要能使用USB-BLASTER的驱动， 那么就需要实现FT245的USB协议。
你需要去FTDI网站下载相关资料。自己肯定要分析USB通讯的协议。
CPLD实现了字节流控制协议。 你需要搞清楚每个BIT的功能和定义， 网上也能找到这些。
等级低， 不能发链接， 附在后面。
虽然是个小东西， 要吃透还是需要自己去学习。
理论上只要带有USB-Device的CPU基本都可以实现USB-BLASTER的功能。即使是51内核的也可以。
usb_jtag firmware now happens to behave just like the combination of
FT245BM and Altera-programmed EPM7064 CPLD in Altera's USB-Blaster.
The CPLD knows two major modes: Bit banging mode and Byte shift mode.
It starts in Bit banging mode. While bytes are received from the host
on EP2OUT, each byte B of them is processed as follows:
Bit banging mode
----------------
1. Remember bit 6 (0x40) in B as the "Read bit".
2. If bit 7 (0x80) is set, switch to Byte shift mode for the coming X
bytes ( X := B & 0x3F ), and don't do anything else now.
3. Otherwise, set the JTAG signals as follows:
- TCK/DCLK high if bit 0 was set (0x01), otherwise low
- TMS/nCONFIG high if bit 1 was set (0x02), otherwise low
- nCE high if bit 2 was set (0x04), otherwise low
- nCS high if bit 3 was set (0x08), otherwise low
- TDI/ASDI/DATAO high if bit 4 was set (0x10), otherwise low
- Output Enable/LED active if bit 5 was set (0x20), otherwise low
4. If "Read bit" (0x40) was set, record the state of TDO(CONF_DONE) and
DATAOUT/(nSTATUS) pins and put is as a byte( (DATAOUT<<1)|TDO) in the
output FIFO _to_ the host.
Byte shift mode
---------------
1. Load shift register with byte from host
2. Do 8 times (i.e. for each bit of the byte; implemented in shift.a51)
- if nCS=1, set carry bit from TDO, else set carry bit from DATAOUT
(Active Serial mode)
- Rotate shift register through carry bit
- TDI := Carry bit
- Raise TCK, then lower TCK.
3. If "Read bit" was set when switching into byte shift mode, record the
shift register content and put it into the FIFO to the host. |
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楼主
LPC4370，记差了，这个比LPC435x更强，80M的ADC啊，做示波器可以省了ADC了
