|
|
楼主 |
发表于 2019-5-14 10:49:54
|
显示全部楼层
我做过类似项目。
按4倍频计数和判相，/4为不倍频输出，/8为二分频输出
能指导下吗，我这个思路是否正确，是否有遗漏的地方。现贴上描述语言，编译通过
module data_shilt(data_in_a,data_in_b,data_a,data_b);
input data_in_a;
input data_in_b;
output data_a;
output data_b;
reg data_a;
reg data_b;
reg [2:0]con1;//a的下降沿
reg [2:0]con2;//a的上升沿
//下降沿negedge
//上升沿posedge
always @(data_in_a)
begin
if(data_in_a==1'b0)
begin
if(con1>=1)//32 or 16
begin
con1=0;
data_a<=1'b1;
end
else
begin
data_a<=1'b0;
data_b<=data_in_b;
con1=1;
con2=0;
end
end
//
else
begin
if(con2>=1)//
begin
con2=0;
data_b<=~data_b;
end
else
begin
data_b<=~data_b;
con2=1;
end
end
end
endmodule
//
//
module data_s_16(a1_in,b1_in,a2_in,b2_in,a1_out,b1_out,a2_out,b2_out);
input a1_in;
input b1_in;
input a2_in;
input b2_in;
//
output a1_out;
output b1_out;
output a2_out;
output b2_out;
//
wire a1_out;
wire b1_out;
wire a2_out;
wire b2_out;
//
data_shilt data_r0(a1_in,b1_in,a1_out,b1_out);
data_shilt data_r1(a2_in,b2_in,a2_out,b2_out);
endmodule
|
|
发表于 2019-5-13 16:04:58
