AT32F403A时钟直接寄存器设置成功频率却没变化

cnxh · 发表于 2022-5-24 21:53:39

因为原代码是stm的不想再改,所以源文件的库都是用的stm的,看到at32f403a的频率可以到200m所以想其它的代码还是用stm一样,只是把频率用AT的库设置到192m,原代码是先用stm的库设置8m,倍频到72m,然后引用M_At32F40X_SystemClock(24),
24倍频到192m,因为直接加入引用at的库时,和stm的有些冲突,所以把at库里用到的枚举和函数复制过来,设置完成后,用stm的库函数RCC_GetClocksFreq(&RCC_ClocksStatus); //读出时钟配置
如果小于17倍,读出的设置频率和设置的一样,大于17反而会变小,如16倍,读出设置的是128M,24倍本来应该倍频到192M的读出反而是64M,但是如果已设置的128M,实际运行的速度却没有,用指示灯闪烁查看
哪位兄度熟点测试下

/**
**************************************************************************
* @file at32f403a_407_clock.c
* @version v2.0.9
* @date 2022-04-25
* @brief system clock config program
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* includes ------------------------------------------------------------------*/
//#include "at32f403a_407_clock.h"
/** @addtogroup AT32F403A_periph_template
* @{
*/
/** @addtogroup 403A_System_clock_configuration System_clock_configuration
* @{
*/
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = hext / 2 * pll_mult
* - system clock source = pll (hext)
* - hext = 8000000
* - sclk = 240000000
* - ahbdiv = 1
* - ahbclk = 240000000
* - apb2div = 2
* - apb2clk = 120000000
* - apb1div = 2
* - apb1clk = 120000000
* - pll_mult = 60
* - pll_range = GT72MHZ (greater than 72 mhz)
* @param none
* @retval none
*/
typedef struct
{
/**
* @brief crm ctrl register, offset:0x00
*/
union
{
__IO uint32_t ctrl;
struct
{
__IO uint32_t hicken : 1; /* [0] */
__IO uint32_t hickstbl : 1; /* [1] */
__IO uint32_t hicktrim : 6; /* [7:2] */
__IO uint32_t hickcal : 8; /* [15:8] */
__IO uint32_t hexten : 1; /* [16] */
__IO uint32_t hextstbl : 1; /* [17] */
__IO uint32_t hextbyps : 1; /* [18] */
__IO uint32_t cfden : 1; /* [19] */
__IO uint32_t reserved1 : 4; /* [23:20] */
__IO uint32_t pllen : 1; /* [24] */
__IO uint32_t pllstbl : 1; /* [25] */
__IO uint32_t reserved2 : 6; /* [31:26] */
} ctrl_bit;
};
/**
* @brief crm cfg register, offset:0x04
*/
union
{
__IO uint32_t cfg;
struct
{
__IO uint32_t sclksel : 2; /* [1:0] */
__IO uint32_t sclksts : 2; /* [3:2] */
__IO uint32_t ahbdiv : 4; /* [7:4] */
__IO uint32_t apb1div : 3; /* [10:8] */
__IO uint32_t apb2div : 3; /* [13:11] */
__IO uint32_t adcdiv_l : 2; /* [15:14] */
__IO uint32_t pllrcs : 1; /* [16] */
__IO uint32_t pllhextdiv : 1; /* [17] */
__IO uint32_t pllmult_l : 4; /* [21:18] */
__IO uint32_t usbdiv_l : 2; /* [23:22] */
__IO uint32_t clkout_sel : 3; /* [26:24] */
__IO uint32_t usbdiv_h : 1; /* [27] */
__IO uint32_t adcdiv_h : 1; /* [28] */
__IO uint32_t pllmult_h : 2; /* [30:29] */
__IO uint32_t pllrange : 1; /* [31] */
} cfg_bit;
};
/**
* @brief crm clkint register, offset:0x08
*/
union
{
__IO uint32_t clkint;
struct
{
__IO uint32_t lickstblf : 1; /* [0] */
__IO uint32_t lextstblf : 1; /* [1] */
__IO uint32_t hickstblf : 1; /* [2] */
__IO uint32_t hextstblf : 1; /* [3] */
__IO uint32_t pllstblf : 1; /* [4] */
__IO uint32_t reserved1 : 2; /* [6:5] */
__IO uint32_t cfdf : 1; /* [7] */
__IO uint32_t lickstblien : 1; /* [8] */
__IO uint32_t lextstblien : 1; /* [9] */
__IO uint32_t hickstblien : 1; /* [10] */
__IO uint32_t hextstblien : 1; /* [11] */
__IO uint32_t pllstblien : 1; /* [12] */
__IO uint32_t reserved2 : 3; /* [15:13] */
__IO uint32_t lickstblfc : 1; /* [16] */
__IO uint32_t lextstblfc : 1; /* [17] */
__IO uint32_t hickstblfc : 1; /* [18] */
__IO uint32_t hextstblfc : 1; /* [19] */
__IO uint32_t pllstblfc : 1; /* [20] */
__IO uint32_t reserved3 : 2; /* [22:21] */
__IO uint32_t cfdfc : 1; /* [23] */
__IO uint32_t reserved4 : 8; /* [31:24] */
} clkint_bit;
};
/**
* @brief crm apb2rst register, offset:0x0C
*/
union
{
__IO uint32_t apb2rst;
struct
{
__IO uint32_t iomuxrst : 1; /* [0] */
__IO uint32_t exintrst : 1; /* [1] */
__IO uint32_t gpioarst : 1; /* [2] */
__IO uint32_t gpiobrst : 1; /* [3] */
__IO uint32_t gpiocrst : 1; /* [4] */
__IO uint32_t gpiodrst : 1; /* [5] */
__IO uint32_t gpioerst : 1; /* [6] */
__IO uint32_t reserved1 : 2; /* [8:7] */
__IO uint32_t adc1rst : 1; /* [9] */
__IO uint32_t adc2rst : 1; /* [10] */
__IO uint32_t tmr1rst : 1; /* [11] */
__IO uint32_t spi1rst : 1; /* [12] */
__IO uint32_t tmr8rst : 1; /* [13] */
__IO uint32_t usart1rst : 1; /* [14] */
__IO uint32_t adc3rst : 1; /* [15] */
__IO uint32_t reserved2 : 3; /* [18:16] */
__IO uint32_t tmr9rst : 1; /* [19] */
__IO uint32_t tmr10rst : 1; /* [20] */
__IO uint32_t tmr11rst : 1; /* [21] */
__IO uint32_t accrst : 1; /* [22] */
__IO uint32_t i2c3rst : 1; /* [23] */
__IO uint32_t usart6rst : 1; /* [24] */
__IO uint32_t uart7rst : 1; /* [25] */
__IO uint32_t uart8rst : 1; /* [26] */
__IO uint32_t reserved3 : 5; /* [31:27] */
} apb2rst_bit;
};
/**
* @brief crm apb1rst register, offset:0x10
*/
union
{
__IO uint32_t apb1rst;
struct
{
__IO uint32_t tmr2rst : 1; /* [0] */
__IO uint32_t tmr3rst : 1; /* [1] */
__IO uint32_t tmr4rst : 1; /* [2] */
__IO uint32_t tmr5rst : 1; /* [3] */
__IO uint32_t tmr6rst : 1; /* [4] */
__IO uint32_t tmr7rst : 1; /* [5] */
__IO uint32_t tmr12rst : 1; /* [6] */
__IO uint32_t tmr13rst : 1; /* [7] */
__IO uint32_t tmr14rst : 1; /* [8] */
__IO uint32_t reserved1 : 2; /* [10:9] */
__IO uint32_t wwdtrst : 1; /* [11] */
__IO uint32_t reserved2 : 2; /* [13:12] */
__IO uint32_t spi2rst : 1; /* [14] */
__IO uint32_t spi3rst : 1; /* [15] */
__IO uint32_t spi4rst : 1; /* [16] */
__IO uint32_t usart2rst : 1; /* [17] */
__IO uint32_t usart3rst : 1; /* [18] */
__IO uint32_t uart4rst : 1; /* [19] */
__IO uint32_t uart5rst : 1; /* [20] */
__IO uint32_t i2c1rst : 1; /* [21] */
__IO uint32_t i2c2rst : 1; /* [22] */
__IO uint32_t usbrst : 1; /* [23] */
__IO uint32_t reserved3 : 1; /* [24] */
__IO uint32_t can1rst : 1; /* [25] */
__IO uint32_t can2rst : 1; /* [26] */
__IO uint32_t bprrst : 1; /* [27] */
__IO uint32_t pwcrst : 1; /* [28] */
__IO uint32_t dacrst : 1; /* [29] */
__IO uint32_t reserved4 : 2; /* [31:30] */
} apb1rst_bit;
};
/**
* @brief crm ahben register, offset:0x14
*/
union
{
__IO uint32_t ahben;
#if defined (AT32F403Axx)
struct
{
__IO uint32_t dma1en : 1; /* [0] */
__IO uint32_t dma2en : 1; /* [1] */
__IO uint32_t sramen : 1; /* [2] */
__IO uint32_t reserved1 : 1; /* [3] */
__IO uint32_t flashen : 1; /* [4] */
__IO uint32_t reserved2 : 1; /* [5] */
__IO uint32_t crcen : 1; /* [6] */
__IO uint32_t reserved3 : 1; /* [7] */
__IO uint32_t xmcen : 1; /* [8] */
__IO uint32_t reserved4 : 1; /* [9] */
__IO uint32_t sdio1en : 1; /* [10] */
__IO uint32_t sdio2en : 1; /* [11] */
__IO uint32_t reserved5 : 20;/* [31:12] */
} ahben_bit;
#endif
#if defined (AT32F407xx)
struct
{
__IO uint32_t dma1en : 1; /* [0] */
__IO uint32_t dma2en : 1; /* [1] */
__IO uint32_t sramen : 1; /* [2] */
__IO uint32_t reserved1 : 1; /* [3] */
__IO uint32_t flashen : 1; /* [4] */
__IO uint32_t reserved2 : 1; /* [5] */
__IO uint32_t crcen : 1; /* [6] */
__IO uint32_t reserved3 : 1; /* [7] */
__IO uint32_t xmcen : 1; /* [8] */
__IO uint32_t reserved4 : 1; /* [9] */
__IO uint32_t sdio1en : 1; /* [10] */
__IO uint32_t sdio2en : 1; /* [11] */
__IO uint32_t reserved5 : 2; /* [13:12] */
__IO uint32_t emacen : 1; /* [14] */
__IO uint32_t emactxen : 1; /* [15] */
__IO uint32_t emacrxen : 1; /* [16] */
__IO uint32_t reserved6 : 11;/* [27:17] */
__IO uint32_t emacptpen : 1; /* [28] */
__IO uint32_t reserved7 : 3; /* [31:29] */
} ahben_bit;
#endif
};
/**
* @brief crm apb2en register, offset:0x18
*/
union
{
__IO uint32_t apb2en;
struct
{
__IO uint32_t iomuxen : 1; /* [0] */
__IO uint32_t reserved1 : 1; /* [1] */
__IO uint32_t gpioaen : 1; /* [2] */
__IO uint32_t gpioben : 1; /* [3] */
__IO uint32_t gpiocen : 1; /* [4] */
__IO uint32_t gpioden : 1; /* [5] */
__IO uint32_t gpioeen : 1; /* [6] */
__IO uint32_t reserved2 : 2; /* [8:7] */
__IO uint32_t adc1en : 1; /* [9] */
__IO uint32_t adc2en : 1; /* [10] */
__IO uint32_t tmr1en : 1; /* [11] */
__IO uint32_t spi1en : 1; /* [12] */
__IO uint32_t tmr8en : 1; /* [13] */
__IO uint32_t usart1en : 1; /* [14] */
__IO uint32_t adc3en : 1; /* [15] */
__IO uint32_t reserved3 : 3; /* [18:16] */
__IO uint32_t tmr9en : 1; /* [19] */
__IO uint32_t tmr10en : 1; /* [20] */
__IO uint32_t tmr11en : 1; /* [21] */
__IO uint32_t accen : 1; /* [22] */
__IO uint32_t i2c3en : 1; /* [23] */
__IO uint32_t usart6en : 1; /* [24] */
__IO uint32_t uart7en : 1; /* [25] */
__IO uint32_t uart8en : 1; /* [26] */
__IO uint32_t reserved4 : 5; /* [31:27] */
} apb2en_bit;
};
/**
* @brief crm apb1en register, offset:0x1C
*/
union
{
__IO uint32_t apb1en;
struct
{
__IO uint32_t tmr2en : 1; /* [0] */
__IO uint32_t tmr3en : 1; /* [1] */
__IO uint32_t tmr4en : 1; /* [2] */
__IO uint32_t tmr5en : 1; /* [3] */
__IO uint32_t tmr6en : 1; /* [4] */
__IO uint32_t tmr7en : 1; /* [5] */
__IO uint32_t tmr12en : 1; /* [6] */
__IO uint32_t tmr13en : 1; /* [7] */
__IO uint32_t tmr14en : 1; /* [8] */
__IO uint32_t reserved1 : 2; /* [10:9] */
__IO uint32_t wwdten : 1; /* [11] */
__IO uint32_t reserved2 : 2; /* [13:12] */
__IO uint32_t spi2en : 1; /* [14] */
__IO uint32_t spi3en : 1; /* [15] */
__IO uint32_t spi4en : 1; /* [16] */
__IO uint32_t usart2en : 1; /* [17] */
__IO uint32_t usart3en : 1; /* [18] */
__IO uint32_t uart4en : 1; /* [19] */
__IO uint32_t uart5en : 1; /* [20] */
__IO uint32_t i2c1en : 1; /* [21] */
__IO uint32_t i2c2en : 1; /* [22] */
__IO uint32_t usben : 1; /* [23] */
__IO uint32_t reserved3 : 1; /* [24] */
__IO uint32_t can1en : 1; /* [25] */
__IO uint32_t can2en : 1; /* [26] */
__IO uint32_t bpren : 1; /* [27] */
__IO uint32_t pwcen : 1; /* [28] */
__IO uint32_t dacen : 1; /* [29] */
__IO uint32_t reserved4 : 2; /* [31:30] */
} apb1en_bit;
};
/**
* @brief crm bpdc register, offset:0x20
*/
union
{
__IO uint32_t bpdc;
struct
{
__IO uint32_t lexten : 1; /* [0] */
__IO uint32_t lextstbl : 1; /* [1] */
__IO uint32_t lextbyps : 1; /* [2] */
__IO uint32_t reserved1 : 5; /* [7:3] */
__IO uint32_t rtcsel : 2; /* [9:8] */
__IO uint32_t reserved2 : 5; /* [14:10] */
__IO uint32_t rtcen : 1; /* [15] */
__IO uint32_t bpdrst : 1; /* [16] */
__IO uint32_t reserved3 : 15;/* [31:17] */
} bpdc_bit;
};
/**
* @brief crm ctrlsts register, offset:0x24
*/
union
{
__IO uint32_t ctrlsts;
struct
{
__IO uint32_t licken : 1; /* [0] */
__IO uint32_t lickstbl : 1; /* [1] */
__IO uint32_t reserved1 : 22;/* [23:2] */
__IO uint32_t rstfc : 1; /* [24] */
__IO uint32_t reserved2 : 1; /* [25] */
__IO uint32_t nrstf : 1; /* [26] */
__IO uint32_t porrstf : 1; /* [27] */
__IO uint32_t swrstf : 1; /* [28] */
__IO uint32_t wdtrstf : 1; /* [29] */
__IO uint32_t wwdtrstf : 1; /* [30] */
__IO uint32_t lprstf : 1; /* [31] */
} ctrlsts_bit;
};
/**
* @brief crm ahbrst register, offset:0x28
*/
union
{
__IO uint32_t ahbrst;
#if defined (AT32F407xx)
struct
{
__IO uint32_t reserved1 : 14;/* [13:0] */
__IO uint32_t emacrst : 1; /* [14] */
__IO uint32_t reserved2 : 17;/* [31:15] */
} ahbrst_bit;
#endif
};
/**
* @brief crm reserved1 register, offset:0x2C
*/
__IO uint32_t reserved1;
/**
* @brief crm misc1 register, offset:0x30
*/
union
{
__IO uint32_t misc1;
struct
{
__IO uint32_t hickcal_key : 8; /* [7:0] */
__IO uint32_t reserved1 : 8; /* [15:8] */
__IO uint32_t clkout_sel : 1; /* [16] */
__IO uint32_t reserved2 : 7; /* [23:17] */
__IO uint32_t usbbufs : 1; /* [24] */
__IO uint32_t hickdiv : 1; /* [25] */
__IO uint32_t reserved3 : 2; /* [27:26] */
__IO uint32_t clkoutdiv : 4; /* [31:28] */
} misc1_bit;
};
/**
* @brief crm reserved2 register, offset:0x4C~0x34
*/
__IO uint32_t reserved2[7];
/**
* @brief crm misc2 register, offset:0x50
*/
union
{
__IO uint32_t misc2;
struct
{
__IO uint32_t reserved1 : 16;/* [15:0] */
__IO uint32_t clk_to_tmr : 1; /* [16] */
__IO uint32_t reserved2 : 15;/* [31:17] */
} misc2_bit;
};
/**
* @brief crm misc3 register, offset:0x54
*/
union
{
__IO uint32_t misc3;
struct
{
__IO uint32_t reserved1 : 4; /* [3:0] */
__IO uint32_t auto_step_en : 2; /* [5:4] */
__IO uint32_t reserved2 : 2; /* [7:6] */
__IO uint32_t hick_to_usb : 1; /* [8] */
__IO uint32_t hick_to_sclk : 1; /* [9] */
__IO uint32_t reserved3 : 2; /* [11:10] */
__IO uint32_t hextdiv : 2; /* [13:12] */
__IO uint32_t reserved4 : 1; /* [14] */
__IO uint32_t emac_pps_sel : 1; /* [15] */
__IO uint32_t reserved5 : 16;/* [31:16] */
} misc3_bit;
};
/**
* @brief crm reserved3 register, offset:0x58
*/
__IO uint32_t reserved3;
/**
* @brief crm intmap register, offset:0x5C
*/
union
{
__IO uint32_t intmap;
struct
{
__IO uint32_t usbintmap : 1; /* [0] */
__IO uint32_t reserved1 : 31;/* [31:1] */
} intmap_bit;
};
} crm_type;
#define CRM ((crm_type *) CRM_BASE)
typedef enum
{
CRM_SCLK_HICK = 0x00, /*!< select high speed internal clock as sclk */
CRM_SCLK_HEXT = 0x01, /*!< select high speed external crystal as sclk */
CRM_SCLK_PLL = 0x02 /*!< select phase locking loop clock as sclk */
} crm_sclk_type;
void crm_reset(void)
{
/* reset the crm clock configuration to the default reset state(for debug purpose) */
/* set hicken bit */
CRM->ctrl_bit.hicken = true;
/* wait hick stable */
while(CRM->ctrl_bit.hickstbl != SET);
/* hick used as system clock */
CRM->cfg_bit.sclksel = CRM_SCLK_HICK;
/* wait sclk switch status */
while(CRM->cfg_bit.sclksts != CRM_SCLK_HICK);
/* reset cfg register, include sclk switch, ahbdiv, apb1div, apb2div, adcdiv,
clkout pllrcs, pllhextdiv, pllmult, usbdiv and pllrange bits */
CRM->cfg = 0;
/* reset hexten, hextbyps, cfden and pllen bits */
CRM->ctrl &= ~(0x010D0000U);
/* reset clkout[3], usbbufs, hickdiv, clkoutdiv */
CRM->misc1 = 0;
/* disable all interrupts enable and clear pending bits */
CRM->clkint = 0x009F0000;
}
/////////////////////////////////////////////////////////////////////////////////////
typedef enum
{
CRM_CLOCK_SOURCE_HICK = 0x00, /*!< high speed internal clock */
CRM_CLOCK_SOURCE_HEXT = 0x01, /*!< high speed external crystal */
CRM_CLOCK_SOURCE_PLL = 0x02, /*!< phase locking loop */
CRM_CLOCK_SOURCE_LEXT = 0x03, /*!< low speed external crystal */
CRM_CLOCK_SOURCE_LICK = 0x04 /*!< low speed internal clock */
} crm_clock_source_type;
typedef enum {FALSE = 0, TRUE = !FALSE} confirm_state;
void crm_clock_source_enable(crm_clock_source_type source, confirm_state new_state)
{
switch(source)
{
case CRM_CLOCK_SOURCE_HICK:
CRM->ctrl_bit.hicken = new_state;
break;
case CRM_CLOCK_SOURCE_HEXT:
CRM->ctrl_bit.hexten = new_state;
break;
case CRM_CLOCK_SOURCE_PLL:
CRM->ctrl_bit.pllen = new_state;
break;
case CRM_CLOCK_SOURCE_LEXT:
CRM->bpdc_bit.lexten = new_state;
break;
case CRM_CLOCK_SOURCE_LICK:
CRM->ctrlsts_bit.licken = new_state;
break;
default:
break;
}
}
/////////////////////////////////////////////////////////
#define REG8(addr) *(volatile uint8_t *)(addr)
#define REG16(addr) *(volatile uint16_t *)(addr)
#define REG32(addr) *(volatile uint32_t *)(addr)
#define CRM_PLL_STABLE_FLAG MAKE_VALUE(0x00, 25) /*!< phase locking loop stable flag */
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define MAKE_VALUE(reg_offset, bit_num) (uint32_t)(((reg_offset) << 16) | (bit_num & 0x1F))
#define CRM_HEXT_STABLE_FLAG MAKE_VALUE(0x00, 17) /*!< high speed external crystal stable flag */
#define PERIPH_REG(periph_base, value) REG32((periph_base + (value >> 16)))
#define PERIPH_REG_BIT(value) (0x1U << (value & 0x1F))
#define CRM_REG_BIT(value) PERIPH_REG_BIT(value)
#define CRM_REG(value) PERIPH_REG(CRM_BASE, value)
bool crm_flag_get(uint32_t flag)
{
bool status = RESET;
if((CRM_REG(flag) & CRM_REG_BIT(flag)) != CRM_REG_BIT(flag))
{
status = RESET;
}
else
{
status = SET;
}
return status;
}
bool crm_hext_stable_wait(void)
{
uint32_t stable_cnt = 0;
bool status = ERROR;
while((crm_flag_get(CRM_HEXT_STABLE_FLAG) != SET) && (stable_cnt < HEXT_STARTUP_TIMEOUT))
{
stable_cnt ++;
}
if(crm_flag_get(CRM_HEXT_STABLE_FLAG) != SET)
{
status = ERROR;
}
else
{
status = SUCCESS;
}
return status;
}
/////////////////////////////////////////////////////
typedef enum
{
CRM_PLL_SOURCE_HICK = 0x00, /*!< high speed internal clock as pll reference clock source */
CRM_PLL_SOURCE_HEXT = 0x01, /*!< high speed external crystal as pll reference clock source */
CRM_PLL_SOURCE_HEXT_DIV = 0x02 /*!< high speed external crystal div as pll reference clock source */
} crm_pll_clock_source_type;
typedef enum
{
CRM_PLL_MULT_2 = 0, /*!< pll multiplication factor 2 */
CRM_PLL_MULT_3 = 1, /*!< pll multiplication factor 3 */
CRM_PLL_MULT_4 = 2, /*!< pll multiplication factor 4 */
CRM_PLL_MULT_5 = 3, /*!< pll multiplication factor 5 */
CRM_PLL_MULT_6 = 4, /*!< pll multiplication factor 6 */
CRM_PLL_MULT_7 = 5, /*!< pll multiplication factor 7 */
CRM_PLL_MULT_8 = 6, /*!< pll multiplication factor 8 */
CRM_PLL_MULT_9 = 7, /*!< pll multiplication factor 9 */
CRM_PLL_MULT_10 = 8, /*!< pll multiplication factor 10 */
CRM_PLL_MULT_11 = 9, /*!< pll multiplication factor 11 */
CRM_PLL_MULT_12 = 10, /*!< pll multiplication factor 12 */
CRM_PLL_MULT_13 = 11, /*!< pll multiplication factor 13 */
CRM_PLL_MULT_14 = 12, /*!< pll multiplication factor 14 */
CRM_PLL_MULT_15 = 13, /*!< pll multiplication factor 15 */
CRM_PLL_MULT_16 = 14, /*!< pll multiplication factor 16 */
CRM_PLL_MULT_17 = 15, /*!< pll multiplication factor 17 */
CRM_PLL_MULT_18 = 16, /*!< pll multiplication factor 18 */
CRM_PLL_MULT_19 = 17, /*!< pll multiplication factor 19 */
CRM_PLL_MULT_20 = 18, /*!< pll multiplication factor 20 */
CRM_PLL_MULT_21 = 19, /*!< pll multiplication factor 21 */
CRM_PLL_MULT_22 = 20, /*!< pll multiplication factor 22 */
CRM_PLL_MULT_23 = 21, /*!< pll multiplication factor 23 */
CRM_PLL_MULT_24 = 22, /*!< pll multiplication factor 24 */
CRM_PLL_MULT_25 = 23, /*!< pll multiplication factor 25 */
CRM_PLL_MULT_26 = 24, /*!< pll multiplication factor 26 */
CRM_PLL_MULT_27 = 25, /*!< pll multiplication factor 27 */
CRM_PLL_MULT_28 = 26, /*!< pll multiplication factor 28 */
CRM_PLL_MULT_29 = 27, /*!< pll multiplication factor 29 */
CRM_PLL_MULT_30 = 28, /*!< pll multiplication factor 30 */
CRM_PLL_MULT_31 = 29, /*!< pll multiplication factor 31 */
CRM_PLL_MULT_32 = 30, /*!< pll multiplication factor 32 */
CRM_PLL_MULT_33 = 31, /*!< pll multiplication factor 33 */
CRM_PLL_MULT_34 = 32, /*!< pll multiplication factor 34 */
CRM_PLL_MULT_35 = 33, /*!< pll multiplication factor 35 */
CRM_PLL_MULT_36 = 34, /*!< pll multiplication factor 36 */
CRM_PLL_MULT_37 = 35, /*!< pll multiplication factor 37 */
CRM_PLL_MULT_38 = 36, /*!< pll multiplication factor 38 */
CRM_PLL_MULT_39 = 37, /*!< pll multiplication factor 39 */
CRM_PLL_MULT_40 = 38, /*!< pll multiplication factor 40 */
CRM_PLL_MULT_41 = 39, /*!< pll multiplication factor 41 */
CRM_PLL_MULT_42 = 40, /*!< pll multiplication factor 42 */
CRM_PLL_MULT_43 = 41, /*!< pll multiplication factor 43 */
CRM_PLL_MULT_44 = 42, /*!< pll multiplication factor 44 */
CRM_PLL_MULT_45 = 43, /*!< pll multiplication factor 45 */
CRM_PLL_MULT_46 = 44, /*!< pll multiplication factor 46 */
CRM_PLL_MULT_47 = 45, /*!< pll multiplication factor 47 */
CRM_PLL_MULT_48 = 46, /*!< pll multiplication factor 48 */
CRM_PLL_MULT_49 = 47, /*!< pll multiplication factor 49 */
CRM_PLL_MULT_50 = 48, /*!< pll multiplication factor 50 */
CRM_PLL_MULT_51 = 49, /*!< pll multiplication factor 51 */
CRM_PLL_MULT_52 = 50, /*!< pll multiplication factor 52 */
CRM_PLL_MULT_53 = 51, /*!< pll multiplication factor 53 */
CRM_PLL_MULT_54 = 52, /*!< pll multiplication factor 54 */
CRM_PLL_MULT_55 = 53, /*!< pll multiplication factor 55 */
CRM_PLL_MULT_56 = 54, /*!< pll multiplication factor 56 */
CRM_PLL_MULT_57 = 55, /*!< pll multiplication factor 57 */
CRM_PLL_MULT_58 = 56, /*!< pll multiplication factor 58 */
CRM_PLL_MULT_59 = 57, /*!< pll multiplication factor 59 */
CRM_PLL_MULT_60 = 58, /*!< pll multiplication factor 60 */
CRM_PLL_MULT_61 = 59, /*!< pll multiplication factor 61 */
CRM_PLL_MULT_62 = 60, /*!< pll multiplication factor 62 */
CRM_PLL_MULT_63 = 61, /*!< pll multiplication factor 63 */
CRM_PLL_MULT_64 = 62 /*!< pll multiplication factor 64 */
} crm_pll_mult_type;
typedef enum
{
CRM_PLL_OUTPUT_RANGE_LE72MHZ = 0x00, /*!< pll clock output range less than or equal to 72mhz */
CRM_PLL_OUTPUT_RANGE_GT72MHZ = 0x01 /*!< pll clock output range greater than 72mhz */
} crm_pll_output_range_type;
void crm_pll_config(crm_pll_clock_source_type clock_source, crm_pll_mult_type mult_value, crm_pll_output_range_type pll_range)
{
/* config pll clock source */
if(clock_source == CRM_PLL_SOURCE_HICK)
{
CRM->cfg_bit.pllrcs = FALSE;
}
else
{
CRM->cfg_bit.pllrcs = TRUE;
if(CRM_PLL_SOURCE_HEXT == clock_source)
{
CRM->cfg_bit.pllhextdiv = FALSE;
}
else
{
CRM->cfg_bit.pllhextdiv = TRUE;
}
}
/* config pll multiplication factor */
CRM->cfg_bit.pllmult_l = (mult_value & 0x0F);
CRM->cfg_bit.pllmult_h = ((mult_value & 0x30) >> 4);
/* config pll output range */
CRM->cfg_bit.pllrange = pll_range;
}
//////////////////////////////////////////////////////
typedef enum
{
CRM_HEXT_DIV_2 = 0x00, /*!< high speed external crystal div2 */
CRM_HEXT_DIV_3 = 0x01, /*!< high speed external crystal div3 */
CRM_HEXT_DIV_4 = 0x02, /*!< high speed external crystal div4 */
CRM_HEXT_DIV_5 = 0x03 /*!< high speed external crystal div5 */
} crm_hext_div_type;
void crm_hext_clock_div_set(crm_hext_div_type value)
{
CRM->misc3_bit.hextdiv = value;
}
////////////////////////////////////////
//
//bool crm_flag_get(uint32_t flag)
//{
// bool status = RESET;
// if((CRM_REG(flag) & CRM_REG_BIT(flag)) != CRM_REG_BIT(flag))
// {
// status = RESET;
// }
// else
// {
// status = SET;
// }
// return status;
//}
///////////////////////////////////////////
typedef enum
{
CRM_AHB_DIV_1 = 0x00, /*!< sclk div1 to ahbclk */
CRM_AHB_DIV_2 = 0x08, /*!< sclk div2 to ahbclk */
CRM_AHB_DIV_4 = 0x09, /*!< sclk div4 to ahbclk */
CRM_AHB_DIV_8 = 0x0A, /*!< sclk div8 to ahbclk */
CRM_AHB_DIV_16 = 0x0B, /*!< sclk div16 to ahbclk */
CRM_AHB_DIV_64 = 0x0C, /*!< sclk div64 to ahbclk */
CRM_AHB_DIV_128 = 0x0D, /*!< sclk div128 to ahbclk */
CRM_AHB_DIV_256 = 0x0E, /*!< sclk div256 to ahbclk */
CRM_AHB_DIV_512 = 0x0F /*!< sclk div512 to ahbclk */
} crm_ahb_div_type;
void crm_ahb_div_set(crm_ahb_div_type value)
{
CRM->cfg_bit.ahbdiv = value;
}
//////////////////////////
typedef enum
{
CRM_APB2_DIV_1 = 0x00, /*!< ahbclk div1 to apb2clk */
CRM_APB2_DIV_2 = 0x04, /*!< ahbclk div2 to apb2clk */
CRM_APB2_DIV_4 = 0x05, /*!< ahbclk div4 to apb2clk */
CRM_APB2_DIV_8 = 0x06, /*!< ahbclk div8 to apb2clk */
CRM_APB2_DIV_16 = 0x07 /*!< ahbclk div16 to apb2clk */
} crm_apb2_div_type;
void crm_apb2_div_set(crm_apb2_div_type value)
{
CRM->cfg_bit.apb2div = value;
}
///////////////////////////////////////
typedef enum
{
CRM_APB1_DIV_1 = 0x00, /*!< ahbclk div1 to apb1clk */
CRM_APB1_DIV_2 = 0x04, /*!< ahbclk div2 to apb1clk */
CRM_APB1_DIV_4 = 0x05, /*!< ahbclk div4 to apb1clk */
CRM_APB1_DIV_8 = 0x06, /*!< ahbclk div8 to apb1clk */
CRM_APB1_DIV_16 = 0x07 /*!< ahbclk div16 to apb1clk */
} crm_apb1_div_type;
void crm_apb1_div_set(crm_apb1_div_type value)
{
CRM->cfg_bit.apb1div = value;
}
////////////////////////////////////////
typedef enum
{
CRM_AUTO_STEP_MODE_DISABLE = 0x00, /*!< disable auto step mode */
CRM_AUTO_STEP_MODE_ENABLE = 0x03 /*!< enable auto step mode */
} crm_auto_step_mode_type;
void crm_auto_step_mode_enable(bool new_state)
{
if(new_state == TRUE)
CRM->misc3_bit.auto_step_en = CRM_AUTO_STEP_MODE_ENABLE;
else
CRM->misc3_bit.auto_step_en = CRM_AUTO_STEP_MODE_DISABLE;
}
////////////////////////////////////////////////
void crm_sysclk_switch(crm_sclk_type value)
{
CRM->cfg_bit.sclksel = value;
}
///////////////////////////////////////////
crm_sclk_type crm_sysclk_switch_status_get(void)
{
return (crm_sclk_type)CRM->cfg_bit.sclksts;
}
/////////////////////////////////////////
#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */
#define HEXT_VALUE ((uint32_t)N_ConfigSys_CrystalOsc) /*!< value of the high speed exernal crystal in hz */
unsigned int system_core_clock = HICK_VALUE; /*!< system clock frequency (core clock) */
void system_core_clock_update(void)
{
uint32_t hext_prediv = 0, pll_mult = 0, pll_mult_h = 0, pll_clock_source = 0, temp = 0, div_value = 0;
crm_sclk_type sclk_source;
static const uint8_t sys_ahb_div_table[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
/* get sclk source */
sclk_source = crm_sysclk_switch_status_get();
switch(sclk_source)
{
case CRM_SCLK_HICK:
if(((CRM->misc3_bit.hick_to_sclk) != RESET) && ((CRM->misc1_bit.hickdiv) != RESET))
system_core_clock = HICK_VALUE * 6;
else
system_core_clock = HICK_VALUE;
break;
case CRM_SCLK_HEXT:
system_core_clock = HEXT_VALUE;
break;
case CRM_SCLK_PLL:
pll_clock_source = CRM->cfg_bit.pllrcs;
{
/* get multiplication factor */
pll_mult = CRM->cfg_bit.pllmult_l;
pll_mult_h = CRM->cfg_bit.pllmult_h;
/* process high bits */
if((pll_mult_h != 0U) || (pll_mult == 15U)){
pll_mult += ((16U * pll_mult_h) + 1U);
}
else
{
pll_mult += 2U;
}
if (pll_clock_source == 0x00)
{
/* hick divided by 2 selected as pll clock entry */
system_core_clock = (HICK_VALUE >> 1) * pll_mult;
}
else
{
/* hext selected as pll clock entry */
if (CRM->cfg_bit.pllhextdiv != RESET)
{
hext_prediv = CRM->misc3_bit.hextdiv;
/* hext clock divided by 2 */
system_core_clock = (HEXT_VALUE / (hext_prediv + 2)) * pll_mult;
}
else
{
system_core_clock = HEXT_VALUE * pll_mult;
}
}
}
break;
default:
system_core_clock = HICK_VALUE;
break;
}
/* compute sclk, ahbclk frequency */
/* get ahb division */
temp = CRM->cfg_bit.ahbdiv;
div_value = sys_ahb_div_table[temp];
/* ahbclk frequency */
system_core_clock = system_core_clock >> div_value;
}
//////////////////////////////////////
//设置时钟,有错误最大只能到17倍频
void M_At32F40X_SystemClock(uint32_t RCC_PLLMul_x )
{
/* reset crm */
crm_pll_mult_type T_bp;
//处理倍频
switch(RCC_PLLMul_x)
{
case 2:
T_bp = CRM_PLL_MULT_2;
break;
case 3:
T_bp = CRM_PLL_MULT_3;
break;
case 4:
T_bp = CRM_PLL_MULT_4;
break;
case 5:
T_bp = CRM_PLL_MULT_5;
break;
case 6:
T_bp = CRM_PLL_MULT_6;
break;
case 7:
T_bp = CRM_PLL_MULT_7;
break;
case 8:
T_bp = CRM_PLL_MULT_8;
break;
case 9:
T_bp = CRM_PLL_MULT_9;
break;
case 10:
T_bp = CRM_PLL_MULT_10;
break;
case 11:
T_bp = CRM_PLL_MULT_11;
break;
case 12:
T_bp = CRM_PLL_MULT_12;
break;
case 13:
T_bp = CRM_PLL_MULT_13;
break;
case 14:
T_bp = CRM_PLL_MULT_14;
break;
case 15:
T_bp = CRM_PLL_MULT_15;
break;
case 16:
T_bp = CRM_PLL_MULT_16;
break;
case 17:
T_bp = CRM_PLL_MULT_17;
break;
case 18:
T_bp = CRM_PLL_MULT_18;
break;
case 19:
T_bp = CRM_PLL_MULT_19;
break;
case 20:
T_bp = CRM_PLL_MULT_20;
break;
case 21:
T_bp = CRM_PLL_MULT_21;
break;
case 22:
T_bp = CRM_PLL_MULT_22;
break;
case 23:
T_bp = CRM_PLL_MULT_23;
break;
case 24:
T_bp = CRM_PLL_MULT_24;
break;
case 25:
T_bp = CRM_PLL_MULT_25;
break;
case 26:
T_bp = CRM_PLL_MULT_26;
break;
case 27:
T_bp = CRM_PLL_MULT_27;
break;
case 28:
T_bp = CRM_PLL_MULT_28;
break;
case 29:
T_bp = CRM_PLL_MULT_29;
break;
case 30:
T_bp = CRM_PLL_MULT_30;
break;
case 31:
T_bp = CRM_PLL_MULT_31;
break;
case 32:
T_bp = CRM_PLL_MULT_32;
break;
case 33:
T_bp = CRM_PLL_MULT_33;
break;
case 34:
T_bp = CRM_PLL_MULT_34;
break;
case 35:
T_bp = CRM_PLL_MULT_35;
break;
case 36:
T_bp = CRM_PLL_MULT_36;
break;
case 37:
T_bp = CRM_PLL_MULT_37;
break;
case 38:
T_bp = CRM_PLL_MULT_38;
break;
case 39:
T_bp = CRM_PLL_MULT_39;
break;
case 40:
T_bp = CRM_PLL_MULT_40;
break;
case 41:
T_bp = CRM_PLL_MULT_41;
break;
case 42:
T_bp = CRM_PLL_MULT_42;
break;
case 43:
T_bp = CRM_PLL_MULT_43;
break;
case 44:
T_bp = CRM_PLL_MULT_44;
break;
case 45:
T_bp = CRM_PLL_MULT_45;
break;
case 46:
T_bp = CRM_PLL_MULT_46;
break;
case 47:
T_bp = CRM_PLL_MULT_47;
break;
case 48:
T_bp = CRM_PLL_MULT_48;
break;
case 49:
T_bp = CRM_PLL_MULT_49;
break;
case 50:
T_bp = CRM_PLL_MULT_50;
break;
case 51:
T_bp = CRM_PLL_MULT_51;
break;
case 52:
T_bp = CRM_PLL_MULT_52;
break;
case 53:
T_bp = CRM_PLL_MULT_53;
break;
case 54:
T_bp = CRM_PLL_MULT_54;
break;
case 55:
T_bp = CRM_PLL_MULT_55;
break;
case 56:
T_bp = CRM_PLL_MULT_56;
break;
case 57:
T_bp = CRM_PLL_MULT_57;
break;
case 58:
T_bp = CRM_PLL_MULT_58;
break;
case 59:
T_bp = CRM_PLL_MULT_59;
break;
case 60:
T_bp = CRM_PLL_MULT_60;
break;
case 61:
T_bp = CRM_PLL_MULT_61;
break;
case 62:
T_bp = CRM_PLL_MULT_62;
break;
case 63:
T_bp = CRM_PLL_MULT_63;
break;
case 64:
T_bp = CRM_PLL_MULT_64;
break;
default:
T_bp = CRM_PLL_MULT_4;
break;
}
/* reset crm */
crm_reset();
/* enable hext */
crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE);
/* wait till hext is ready */
while(crm_hext_stable_wait() == ERROR)
{
}
/* config pll clock resource */
crm_pll_config(CRM_PLL_SOURCE_HEXT, T_bp, CRM_PLL_OUTPUT_RANGE_GT72MHZ);
/* enable pll */
crm_clock_source_enable(CRM_CLOCK_SOURCE_PLL, TRUE);
/* wait till pll is ready */
while(crm_flag_get(CRM_PLL_STABLE_FLAG) != SET)
{
}
/* config ahbclk */
crm_ahb_div_set(CRM_AHB_DIV_1);
/* config apb2clk */
crm_apb2_div_set(CRM_APB2_DIV_2);
/* config apb1clk */
crm_apb1_div_set(CRM_APB1_DIV_2);
/* enable auto step mode */
crm_auto_step_mode_enable(TRUE);
/* select pll as system clock source */
crm_sysclk_switch(CRM_SCLK_PLL);
/* wait till pll is used as system clock source */
while(crm_sysclk_switch_status_get() != CRM_SCLK_PLL)
{
}
/* disable auto step mode */
crm_auto_step_mode_enable(FALSE);
/* update system_core_clock global variable */
system_core_clock_update();
}

复制代码

我是一个大白菜 · 发表于 2022-5-24 22:07:29

我用的403a，没有研究过怎么把stm32的移植过来，直接用的at给的例子，跑240M还可以。文档里的第10页有一个pll说明，你可以参考一下

cnxh · 发表于 2022-5-24 22:11:16

我是一个大白菜发表于 2022-5-24 22:07
我用的403a，没有研究过怎么把stm32的移植过来，直接用的at给的例子，跑240M还可以。文档里的第10页有一个p ...
(引用自2楼)

谢谢,我试试,现在设置代码是用他的哪个自动生成时钟代码的软件自动生成,我看了一下生成的代码和网上的代码一样

cnxh · 发表于 2022-5-24 22:23:58

我是一个大白菜发表于 2022-5-24 22:07
我用的403a，没有研究过怎么把stm32的移植过来，直接用的at给的例子，跑240M还可以。文档里的第10页有一个p ...
(引用自2楼)

system_at32f4xx.c这个文件哪里下载,我官网下载的库文件里面的system_at32f403a_407.c文件,内容和网上看到的截图里的部分代码,完全不同,里面也没有pdf说的static void SetSysClockTo168()函数

我是一个大白菜 · 发表于 2022-5-25 00:36:09

cnxh 发表于 2022-5-24 22:23
system_at32f4xx.c这个文件哪里下载,我官网下载的库文件里面的system_at32f403a_407.c文件,内容和网上看 ...
(引用自4楼)

官网升级了一次库，2.xx之后我觉得不好用，原来1.xx的类似stm的库，我比较顺手，我上传你看看，是不是你想要的

cnxh · 发表于 2022-5-25 07:49:28

我是一个大白菜发表于 2022-5-25 00:36
官网升级了一次库，2.xx之后我觉得不好用，原来1.xx的类似stm的库，我比较顺手，我上传你看看，是不是你 ...
(引用自5楼)

太谢谢了

mypear · 发表于 2022-5-25 08:39:38

我是一个大白菜发表于 2022-5-24 22:07
我用的403a，没有研究过怎么把stm32的移植过来，直接用的at给的例子，跑240M还可以。文档里的第10页有一个p ...
(引用自2楼)

原来很多人都在用，我也再用421同最近437测试替换407

我是一个大白菜 · 发表于 2022-5-25 09:08:42

mypear 发表于 2022-5-25 08:39
原来很多人都在用，我也再用421同最近437测试替换407
(引用自7楼)

软件库感觉还是支持的可以的，403a的dma灵活配置感觉比较好用，各个外设基本上都用上dma了，速度快很多

cnxh · 发表于 2022-5-26 19:11:38

本帖最后由 cnxh 于 2022-5-26 19:21 编辑

下面的代码把72M的改成192M,参照pdf的说明,怎么频率还是不对和老的一样
73 85 98行处加入pdf的说的代码,试过RCC_CFG_PLLMULT17 RCC_CFG_PLLMULT20 ,都不正确,其它的pdf上没找到定义,没试

static void SetSysClockTo192(void)
{
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
/* Enable HSE */
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
RCC->CR |= ((uint32_t)RCC_CR_HSEBYP); //外置晶振
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CR & RCC_CR_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CR & RCC_CR_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
//如果进入HSEStatus = (uint32_t)0x01;则外置有源晶振成功起振，如果进入
//HSEStatus = (uint32_t)0x00;则未成功起振，然后会自动切换成HSI。
if (HSEStatus == (uint32_t)0x01)
{
/* Enable Prefetch Buffer */
FLASH->ACR |= FLASH_ACR_PRFTBE;
/* Flash 2 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
/* HCLK = SYSCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
#ifdef STM32F10X_CL
#error ("STM32F10X_CL")
// /* Configure PLLs ------------------------------------------------------*/
// /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
// /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
//
// RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
// RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
// RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
// RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
//
// /* Enable PLL2 */
// RCC->CR |= RCC_CR_PLL2ON;
// /* Wait till PLL2 is ready */
// while((RCC->CR & RCC_CR_PLL2RDY) == 0)
// {
// }
//
//
// /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
// RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
// RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
// RCC_CFGR_PLLMULL9);
#else
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |RCC_CFGR_PLLMULL));
/* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
// RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);//stm32的去掉
//---------------------------------AT32F403A加入
//192M
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFG_PLLMULT20 |RCC_CFG_PLLRANGE_GT72MHZ);
#endif /* STM32F10X_CL */
/* Enable PLL */
RCC->CR |= RCC_CR_PLLON;
/* Wait till PLL is ready */
while((RCC->CR & RCC_CR_PLLRDY) == 0)
{
}
//---------------------------------AT32F403A加入
*((unsigned int *)0x40021054) |= (0x30);// 开启自动滑顺频率切换功能
//#endif
/* Select PLL as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
/* Wait till PLL is used as system clock source */
//#if N_ConfigSys_Debug != true //是否整个程序调试状态
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
{
}
//#endif
//---------------------------------AT32F403A加入
//此时不需再等待200us
*((unsigned int *)0x40021054) &=~ (0x30); //关闭自动滑顺频率切换功能
}
else
{ /* If HSE fails to start-up, the application will have wrong clock
configuration. User can add here some code to deal with this error */
}
}

复制代码

cnxh · 发表于 2022-5-26 21:59:52

搞不定,没办法,只能把设置时钟的做成库然后加入到文件中调用

我是一个大白菜 · 发表于 2022-5-26 22:13:17

cnxh 发表于 2022-5-26 19:11
下面的代码把72M的改成192M,参照pdf的说明,怎么频率还是不对和老的一样
73 85 98行处加入pdf的说的代码,试 ...
(引用自9楼)

你的晶振怎么配置的，在文件 at32f4xx.h 中，下面是我的

/**
* @brief In the following line adjust the value of External High Speed oscillator (HSE)
used in your application
Tip: To avoid modifying this file each time you need to use different HSE, you
can define the HSE value in your toolchain compiler preprocessor.
*/
#if !defined HSE_VALUE
//#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
#define HSE_VALUE ((uint32_t)16000000) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */

复制代码

cnxh · 发表于 2022-5-27 07:19:16

我是一个大白菜发表于 2022-5-26 22:13
你的晶振怎么配置的，在文件 at32f4xx.h 中，下面是我的
(引用自11楼)

谢谢,默认8M

cnxh · 发表于 2022-5-27 07:22:49

本帖最后由 cnxh 于 2022-5-27 07:26 编辑

编译成库,测试工程用c,可以了,现在有个问题,我的工程是c++的,加入调用就会出错,原来测试的c工程可以,把他改成c++,也一样会出错,应该是找不到这个库里的函数,调用时加入extern "C" {}也一样,库函数编译时改成c++也一样
提示 Error[Pe020]: identifier "system_clock_config" is undefined N:\Project\CP1C36\App\1000\App\main.c 327

可以了,加入了声明extern void system_clock_config(void);就可以了

cnxh · 发表于 2022-5-27 07:59:36

上传给也有同样需求的人,已弄好的库文件,加入到工程就可以了,然后主程序调用
extern "C" {
extern void system_clock_config(void);
void gg(void)
{
system_clock_config();
}
}

kingfa021 · 发表于 2023-3-2 20:05:52

cnxh 发表于 2022-5-27 07:59
上传给也有同样需求的人,已弄好的库文件,加入到工程就可以了,然后主程序调用
extern "C" {
extern void s ...
(引用自14楼)

请教一下，碰到同样的问题，下载您这个文件打开是.a文件，貌似打不开，请指教谢谢！

cnxh · 发表于 2023-3-3 19:56:03

kingfa021 发表于 2023-3-2 20:05
请教一下，碰到同样的问题，下载您这个文件打开是.a文件，貌似打不开，请指教谢谢！ ...
(引用自15楼)

不好意思,我自己都忘了怎么弄,现在还是用stm的72m,因为实际运行起来比72m还慢

ddcour · 发表于 2023-3-5 06:52:01

请教一下，这些仿制的，防破解怎样？

tclg · 发表于 2023-3-5 11:06:53

这个改动寄存器即可，雅特力把ST的PLL设置寄存器里，没用到的30:29位用起来了。

AT32F403A时钟直接寄存器设置成功频率却没变化

阿莫论坛20周年了！感谢大家的支持与爱护！！

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