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发表于 2008-3-19 23:28:48
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呵呵，果然是破解。不知道下面的连接对你有没有帮助？但我想你应该google过了
http://download.savannah.gnu.org/releases/freeice/AVR-OCD-Documentation.html
AVR JTAG OCD (Private) Commands
Document Date 05 April 2003
JTAG Instruction 0x08 - Force Break
JTAG Instruction 0x09 - Run
JTAG Instruction 0x0A - Execute AVR Instruction (2 Words!)
use 0x0A, SDR 0xFFFF0000 to read PC (actually returns PC+2 or PC+4)
JTAG Instruction 0x0B - Access OCD Registers
there are total 16 Addressable Registers
after IR next DRSHIFT is RW Flag (1=Write) + 4 Bits Address
those Data in Instruction is 21 (5 + 16) bits
note for read operation OCD Address need to be pre latched!
Register 0 PSB0
Register 1 PSB1
Register 2 PDMSB
Register 3 PDSB
Register 8 Break Control Register (BCR)
Bit rw Description
D15 rw 1=Enable Timers to Run during Break
D14 rw 1=PC is read as +4 not +2 after break ?
D13 rw 1=Break on change Flow ?!
D12 rw 1=Enable PSB0
D11 rw 1=Enable PSB1
D10 rw 1=Enable PDMSB as single break
D9 rw 1=Enable Mask in Break Comparison
D8 rw 1=
D7 rw 1=*
D6 rw 1=
D5 rw 1=
D4 rw 1=*
D3 rw 1=*
D2 rw 1=
D1-0 r (read as 0)
* note when D7, D4, D3 are all set then PDSB is enabled s Program Break
Register 9 - Break Status Register (BSR)
Bit rw Description
D15-D8 r
D7 r 1=Break on change flow
D6 r 1=Break on PSB0 (Reg0)
D5 r 1=Break on PSB1 (Reg1)
D4 r 1=Break on PDMSB (Reg2 as single break)
D3 r 1=Break on PDSB (Reg3)
D2 r 1=Break on ? (has been seen)
D1 r 1=Break forced by OCD (Instr 8)
D0 r 1=Break by AVR Break Instruction (0x9598)
Register C - OCDR Readback
Bit rw Description
D15-8 rw OCDR 7..0
D7-0 r unused (read as 0)
Register D - Control and Status Register
Bit rw Description
D15 rw 1=Enable OCDR
D14 rw 1=?
D13-D5 r
D4 r 1=OCDR written by AVR and not read by OCD
D3 r 1=Reset not active
D2 r 1=Reset not active
D1-0 r |
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楼主: Gorgon_Meducer
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