|
楼主 |
发表于 2009-7-10 11:03:58
|
显示全部楼层
[Warning]:INFO:Cpld - Inferring BUFG constraint for signal 'nCLKIN' based upon the LOC constraint 'P38'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored.
[Warning]:Cpld:896 - Unable to map all desired signals into function block, FB1, because too many function block product terms are required. Buffering output signal UART_DATA<7> to allow all signals assigned to this function block to be placed.
[Warning]:Cpld:896 - Unable to map all desired signals into function block, FB1, because too many function block product terms are required. Buffering output signal UART_DATA<6> to allow all signals assigned to this function block to be placed.
请问上面的警告怎么去除啊 ! |
|