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楼主 |
发表于 2009-7-20 21:43:34
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CPLD描述改为Verilog HDL：（有不对的么？）
//-----------------------------------------------------------------------------
// Serial/Parallel converter, interfacing JTAG chain with FTDI FT245BM
//-----------------------------------------------------------------------------
// Copyright (C) 2005-2007 Kolja Waschk, ixo.de
//-----------------------------------------------------------------------------
// This code is part of usbjtag. usbjtag is free software; you can redistribute
// it and/or modify it under the terms of the GNU General Public License as
// published by the Free Software Foundation; either version 2 of the License,
// or (at your option) any later version. usbjtag is distributed in the hope
// that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details. You should have received a
// copy of the GNU General Public License along with this program in the file
// COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin
// St, Fifth Floor, Boston, MA 02110-1301 USA
//-----------------------------------------------------------------------------
//LIBRARY ieee;
//USE ieee.std_logic_1164.all;
//USE ieee.std_logic_unsigned.all;
//-----------------------------------------------------------------------------
//Verilog HDL Version.
//Converted by helloshi
//Interfacing JTAG chain with FTDI FT245RL and EPM240T100C5
module jtag_logic(CLK,nRXF,nTXE,B_TDO,B_ASDO,B_TCK,B_TMS,B_NCE,B_NCS,B_TDI,B_OE,nRD,WR,D);
input CLK ; // external 24/25 MHz oscillator
input nRXF ; // FT245RL nRXF
input nTXE ; // FT245RL nTXE
input B_TDO ; // JTAG input: TDO, AS/PS input: CONF_DONE
input B_ASDO ; // AS input: DATAOUT, PS input: nSTATUS
output reg B_TCK ; // JTAG output: TCK to chain, AS/PS DCLK
output reg B_TMS ; // JTAG output: TMS to chain, AS/PS nCONFIG
output reg B_NCE ; // AS output: nCE
output reg B_NCS ; // AS output: nCS
output reg B_TDI ; // JTAG output: TDI to chain, AS: ASDI, PS: DATA0
output reg B_OE ; // LED output/output driver enable
output reg nRD ; // FT245RL nRD
output reg WR ; // FT245RL WR
inout reg [7:0]D; // FT245RL D[7..0]
// There are exactly 16 states. If this is encoded using 4 bits, there will
// be no unknown/undefined state. The host will send us 64 times "0" to move
// the state machine to a known state. We don't need a power-on reset.
parameter // states;
wait_for_nRXF_low = 4'b0000,
set_nRD_low = 4'b0001,
keep_nRD_low = 4'b0010,
latch_data_from_host = 4'b0011,
set_nRD_high = 4'b0100,
bits_set_pins_from_data = 4'b0101,
bytes_set_bitcount = 4'b0110,
bytes_get_tdo_set_tdi = 4'b0111,
bytes_clock_high_and_shift = 4'b1000,
bytes_keep_clock_high = 4'b1001,
bytes_clock_finish = 4'b1010,
wait_for_nTXE_low = 4'b1011,
set_WR_high = 4'b1100,
output_enable = 4'b1101,
set_WR_low = 4'b1110,
output_disable = 4'b1111;
reg carry;
reg do_output;
reg [7:0]ioshifter;
reg [8:0]bitcount;
reg [4:0]state, next_state; // states;
always @(CLK, nRXF, nTXE, state, bitcount, ioshifter, do_output) //sm: PROCESS
begin
case (state)
// ============================ INPUT
wait_for_nRXF_low :
if (nRXF == 1'b0)
next_state <= set_nRD_low;
else
next_state <= wait_for_nRXF_low;
set_nRD_low :
next_state <= keep_nRD_low;
keep_nRD_low :
next_state <= latch_data_from_host;
latch_data_from_host :
next_state <= set_nRD_high;
set_nRD_high :
if (bitcount[8:3] != 6'b000000)
next_state <= bytes_get_tdo_set_tdi;
else if (ioshifter[7] == 1'b1)
next_state <= bytes_set_bitcount;
else
next_state <= bits_set_pins_from_data;
bytes_set_bitcount :
next_state <= wait_for_nRXF_low;
// ============================ BIT BANGING
bits_set_pins_from_data :
if (ioshifter[6] == 1'b0)
next_state <= wait_for_nRXF_low; // read next byte from host
else
next_state <= wait_for_nTXE_low; // output byte to host
// ============================ BYTE OUTPUT (SHIFT OUT 8 BITS)
bytes_get_tdo_set_tdi :
next_state <= bytes_clock_high_and_shift;
bytes_clock_high_and_shift :
next_state <= bytes_keep_clock_high;
bytes_keep_clock_high :
next_state <= bytes_clock_finish;
bytes_clock_finish :
if (bitcount[2:0] != 3'b111)
next_state <= bytes_get_tdo_set_tdi; // clock next bit
else if (do_output == 1'b1)
next_state <= wait_for_nTXE_low; // output byte to host
else
next_state <= wait_for_nRXF_low; // read next byte from host
// ============================ OUTPUT BYTE TO HOST
wait_for_nTXE_low :
if (nTXE == 1'b0)
next_state <= set_WR_high;
else
next_state <= wait_for_nTXE_low;
set_WR_high :
next_state <= output_enable;
output_enable :
next_state <= set_WR_low;
set_WR_low :
next_state <= output_disable;
output_disable :
next_state <= wait_for_nRXF_low; // read next byte from host
default :
next_state <= wait_for_nRXF_low;
endcase
end // PROCESS sm;
//always @(posedge CLK, state, ioshifter, B_TDO, bitcount, carry) //out_sm: PROCESS
always @(posedge CLK) //out_sm: PROCESS
begin
//if CLK = '1' AND CLK'event THEN
if (state == set_nRD_low || state == keep_nRD_low || state == latch_data_from_host )
nRD <= 1'b0;
else
nRD <= 1'b1;
if (state == latch_data_from_host)
ioshifter[7:0] <= D;
if (state == set_WR_high || state == output_enable)
WR <= 1'b1;
else
WR <= 1'b0;
if (state == output_enable || state == set_WR_low )
D[7:0] <= ioshifter[7:0];
else
D[7:0] <= 8'bzzzzzzzz;
if (state == bits_set_pins_from_data )
begin
B_TCK <= ioshifter[0];
B_TMS <= ioshifter[1];
B_NCE <= ioshifter[2];
B_NCS <= ioshifter[3];
B_TDI <= ioshifter[4];
B_OE <= ioshifter[5];
ioshifter <= {6'b000000 , B_ASDO , B_TDO};
end
if (state == bytes_set_bitcount )
begin
bitcount <= {ioshifter[5:0] , 3'b111};
do_output <= ioshifter[6];
end
if (state == bytes_get_tdo_set_tdi )
begin
if (B_NCS == 1'b1)
carry <= B_TDO; // JTAG mode (nCS=1)
else
carry <= B_ASDO; // Active Serial mode (nCS=0)
B_TDI <= ioshifter[0];
bitcount <= bitcount - 9'b000000001;
end
if (state == bytes_clock_high_and_shift || state == bytes_keep_clock_high )
B_TCK <= 1'b1;
if (state == bytes_clock_high_and_shift )
ioshifter <= {carry , ioshifter[7:1]};
if (state == bytes_clock_finish )
B_TCK <= 1'b0;
state <= next_state;
end
endmodule |
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发表于 2009-7-14 09:58:29
