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发表于 2009-10-13 14:49:19
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LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
USE IEEE.Std_Logic_Arith.ALL;
USE IEEE.Std_Logic_Unsigned.ALL;
entity My_Lhx is
port (clk_1M,I1,I2,I6,I4,I3:IN Std_Logic;
O1,O2,O6,Ot4,O3:Out Std_Logic);
end My_Lhx;
architecture inference of My_Lhx is
signal C1:Std_Logic_Vector(11 Downto 0);
signal C2:Std_Logic_Vector(11 Downto 0);
signal C6:Std_Logic_Vector(11 Downto 0);
signal C4:Std_Logic_Vector(11 Downto 0);
signal C3:Std_Logic_Vector(11 Downto 0);
signal R1:Std_Logic_Vector(11 Downto 0);
signal R2:Std_Logic_Vector(11 Downto 0);
signal R6:Std_Logic_Vector(11 Downto 0);
signal R4:Std_Logic_Vector(11 Downto 0);
signal R3:Std_Logic_Vector(11 Downto 0);
signal T1:Std_Logic_Vector(7 Downto 0);
signal T2:Std_Logic_Vector(7 Downto 0);
signal T6:Std_Logic_Vector(7 Downto 0);
signal T4:Std_Logic_Vector(7 Downto 0);
signal T3:Std_Logic_Vector(7 Downto 0);
signal J1:Std_Logic_Vector(11 Downto 0);
signal J2:Std_Logic_Vector(11 Downto 0);
signal J6:Std_Logic_Vector(11 Downto 0);
signal J3:Std_Logic_Vector(11 Downto 0);
signal J4:Std_Logic_Vector(11 Downto 0);
signal Wr1,Wr2,Wr6,Wr4,Wr3:Std_Logic;
begin
Ot4 <= Wr4;
process (clk_1M)
begin
if (clk_1M'EVENT and clk_1M='1') then
if (I1 = '0') then
T1 <= T1 + '1';
if (T1 = Conv_Std_Logic_Vector(252,8) and C1 > Conv_Std_Logic_Vector(511,12)) then
Wr1 <= '1';
R1 <= C1;
else
Wr1 <= '0';
end if;
if (T1 > Conv_Std_Logic_Vector(254,8)) then
C1 <= "000000000000";
end if;
else
C1 <= C1 + '1';
T1 <= "00000000";
Wr1 <= '0';
end if; -- END Part Input 1#
if (I2 = '0') then
T2 <= T2 + '1';
if (T2 = Conv_Std_Logic_Vector(252,8) and C2 > Conv_Std_Logic_Vector(511,12)) then
Wr2 <= '1';
R2 <= C2;
else
Wr2 <= '0';
end if;
if (T2 > Conv_Std_Logic_Vector(254,8)) then
C2 <= "000000000000";
end if;
else
C2 <= C2 + '1';
T2 <= "00000000";
Wr2 <= '0';
end if; -- END Part Input 2#
if (I6 = '0') then
T6 <= T6 + '1';
if (T6 = Conv_Std_Logic_Vector(252,8) and C6 > Conv_Std_Logic_Vector(511,12)) then
Wr6 <= '1';
R6 <= C6;
else
Wr6 <= '0';
end if;
if (T6 > Conv_Std_Logic_Vector(254,8)) then
C6 <= "000000000000";
end if;
else
C6 <= C6 + '1';
T6 <= "00000000";
Wr6 <= '0';
end if; -- END Part Input 6#
if (I4 = '0') then
T4 <= T4 + '1';
if (T4 = Conv_Std_Logic_Vector(252,8) and C4 > Conv_Std_Logic_Vector(511,12)) then
Wr4 <= '1';
R4 <= Conv_Std_Logic_Vector((375 - Conv_Integer(C4)/4),12);
else
Wr4 <= '0';
end if;
if (T4 > Conv_Std_Logic_Vector(254,8)) then
C4 <= "000000000000";
end if;
else
C4 <= C4 + '1';
T4 <= "00000000";
Wr4 <= '0';
end if; -- END Part Input 4#
if (I3 = '0') then
T3 <= T3 + '1';
if (T3 = Conv_Std_Logic_Vector(252,8) and C3 > Conv_Std_Logic_Vector(511,12)) then
Wr3 <= '1';
R3 <= C3;
else
Wr3 <= '0';
end if;
if (T3 > Conv_Std_Logic_Vector(254,8)) then
C3 <= "000000000000";
end if;
else
C3 <= C3 + '1';
T3 <= "00000000";
Wr3 <= '0';
end if; -- END Part Input 3#
end if;
end process;
process (Wr1,clk_1M)
begin
if (Wr1 = '1') then
J1 <= R1 - R4;
elsif (clk_1M'EVENT and clk_1M='1') then
if (J1 = "000000000000") then
O1 <= '0';
else
O1 <= '1';
J1 <= J1 - '1';
end if;
end if;
end process;
process (Wr2,clk_1M)
begin
if (Wr2 = '1') then
J2 <= R2 + R4;
elsif (clk_1M'EVENT and clk_1M='1') then
if (J2 = "000000000000") then
O2 <= '0';
else
O2 <= '1';
J2 <= J2 - '1';
end if;
end if;
end process;
process (Wr6,clk_1M)
begin
if (Wr6 = '1') then
J6 <= R6 + R4;
elsif (clk_1M'EVENT and clk_1M='1') then
if (J6 = "000000000000") then
O6 <= '0';
else
O6 <= '1';
J6 <= J6 - '1';
end if;
end if;
end process;
process (R3)
begin
if (R4(11) = '0') then -- LuoJu '-'
J4 <= R3 + Conv_Std_Logic_Vector((Conv_Integer(R4)/2),12); -- YouMen +
else -- LuoJu '+',Youmen No Change
J4 <= R3;
end if;
end process;
process (Wr3,clk_1M)
begin
if (Wr3 = '1') then
J3 <= J4; -- Youmen Use J4 Not R3
elsif (clk_1M'EVENT and clk_1M='1') then
if (J3 = "000000000000") then
O3 <= '0';
else
O3 <= '1';
J3 <= J3 - '1';
end if;
end if;
end process;
end inference;
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