vhdl 两个四位二进制数相乘问题

chahu1227

程序源码如下：

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY muljux4 IS
PORT(a:IN STD_LOGIC_VECTOR(4 DOWNTO 1);
     b:IN STD_LOGIC_VECTOR(4 DOWNTO 1);
     product:OUT STD_LOGIC_VECTOR(8 DOWNTO 1));
END muljux4;
ARCHITECTURE arc OF muljux4 IS
SIGNAL acc,sal:BIT_VECTOR(8 DOWNTO 1);
SIGNAL a1,b1:BIT_VECTOR(4 DOWNTO 1);
SIGNAL in_sal:STD_LOGIC_VECTOR(8 DOWNTO 1);
SIGNAL y:STD_LOGIC_VECTOR(8 DOWNTO 1);   
BEGIN
PROCESS(a,b)
     BEGIN
     a1<=TO_BITVECTOR(a);
     b1<=TO_BITVECTOR(b);
--- product<="00000000";
--- acc<="00000000";
----y<="00000000";
----sal<="00000000";
     FOR i IN 1 TO 4 LOOP
        FOR j IN 1 TO 4 LOOP
        acc(j)<=(a1(j)) AND (b1(i));
        END LOOP ;
     sal<=acc SLL (i-1);
     in_sal<=TO_STDLOGICVECTOR(sal);
     y<=y + in_sal;
     END LOOP;
     product<=y;
   END PROCESS;
END arc;

程序不报错，但输出为0，不知何故，希望高手解答,不胜感激！

ngzhang

module mul4x4 (
  a,
  b,
  c
  )
input [3:0]a,b;
output [7:0]c;

assign c=a*b;

endmodule

zhangchanggong

y<=y + in_sal;这句有问题吧
算法对，好像是综合8位加法器时出问题的
我看没必要弄了，参考下面程序吧

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY mult4 IS PORT (
a,b : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prod : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END mult4;
ARCHITECTURE maxcpld OF mult4 IS
CONSTANT n:INTEGER :=4;
SUBTYPE PART IS STD_LOGIC_VECTOR(n-1 DOWNTO 0);
TYPE PARTS IS ARRAY(0 TO 4) OF PART;
SIGNAL pp,pc,ps:PARTS;
BEGIN
pgen:FOR j IN 0 TO n-1 GENERATE
pgen1:FOR k IN 0 TO n-1 GENERATE
pp(j)(k)<=a(k) AND b(j);
END GENERATE;
pc(0)(J)<='0';
END GENERATE;
pp(4)(3)<='0';
pp(4)(2)<='0';
pp(4)(1)<='0';
pp(4)(0)<='0';
ps(0)<=pp(0);
prod(0)<=pp(0)(0);
addr:FOR j IN 1 TO n-1 GENERATE
addc:FOR k IN 0 TO n-2 GENERATE
ps(j)(k)<=pp(j)(k) XOR pc(j-1)(k) XOR ps(j-1)(k+1);
pc(j)(k)<=(pp(j)(k) AND pc(j-1)(k)) OR (pp(j)(k) AND ps(j-1)(k+1)) OR (pc(j-1)(k) AND ps(j-1)(k+1));
END GENERATE;
prod(j)<=ps(j)(0);
ps(j)(n-1)<=pp(j)(n-1);
END GENERATE;
pc(1)(3)<='0';
pc(2)(3)<='0';
pc(3)(3)<='0';
ps(4)(0)<='0';
pc(n)(0)<='0';
addlast:FOR k IN 1 TO n-1 GENERATE
ps(n)(k)<=pc(n)(k-1) XOR pc(n-1)(k-1) XOR ps(n-1)(k);
pc(n)(k)<=(pc(n)(k-1) AND pc(n-1)(k-1)) OR (pc(n)(k-1) AND ps(n-1)(k)) OR (pc(n-1)(k-1) AND ps(n-1)(k));
END GENERATE;
prod(2*n-1)<=pc(n)(n-1);
prod(2*n-2 DOWNTO n)<=ps(n)(n-1 DOWNTO 1);
END maxcpld;

zhangchanggong

載入STD_LOGIC_ARITH与STD_LOGIC_UNSIGNED元件盒之後，可以直接進行乘法運算
位元数多的乘法器还是从高阶写吧，像徒手相乘的乘法器結构能懂就行了吧，我觉没必要深究，实用就行，又不是写论文！
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY M4 IS PORT (
a,b : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
y : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);END M4;
ARCHITECTURE MAXCPLD OF M4 IS
BEGIN
y(7 DOWNTO 0) <= a(3 DOWNTO 0)*b(3 DOWNTO 0);

END MAXCPLD;
--带符号
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY M4 IS PORT (
a,b : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
y : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
);END M4;
ARCHITECTURE MAXCPLD OF M4 IS
BEGIN
y(7 DOWNTO 0) <= a(3 DOWNTO 0)*b(3 DOWNTO 0);
y(8) <= a(4) XOR b(4);
END MAXCPLD;

chahu1227

谢谢，虽然还没明白，但也懂了其他的实现方法