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部分代码如下:
module con12(Reset,fin,cout,fout);
input Reset,fin;
output cout,fout;
reg cout;
reg [3:0] fout;
always @(posedge fin)
if(!Reset && fout<12)
begin
fout = fout+1;
if(fout==10) cout=1;
else cout=0;
end
else
fout = 0;
endmodule
module count1(Fx,Rst,fx1out,fx2out,fx3out,fx4out);
input Fx,Rst;
output fx1out,fx2out,fx3out,fx4out;
reg [3:0] fx1out,fx2out,fx3out,fx4out;
wire [3:0] c1out,c2out,c3out,c4out;
con12 C1(.fin(Fx),.cout(c1out),.fout(fx1out)); ---line 7
con12 C2(.fin(c1out),.cout(c2out),.fout(fx2out)); ---line 8
con12 C3(.fin(c2out),.cout(c3out),.fout(fx3out)); ---line 9
con12 C4(.fin(c3out),.cout(),.fout(fx4out)); ---line 10
endmodule
编译提示:
ERROR:HDLCompilers:246 - "count1.v" line 7 Reference to vector reg 'fx1out' is not a legal net lvalue
ERROR:HDLCompilers:102 - "count1.v" line 7 Connection to output port 'fout' must be a net lvalue
ERROR:HDLCompilers:246 - "count1.v" line 8 Reference to vector reg 'fx2out' is not a legal net lvalue
ERROR:HDLCompilers:102 - "count1.v" line 8 Connection to output port 'fout' must be a net lvalue
ERROR:HDLCompilers:246 - "count1.v" line 9 Reference to vector reg 'fx3out' is not a legal net lvalue
ERROR:HDLCompilers:102 - "count1.v" line 9 Connection to output port 'fout' must be a net lvalue
ERROR:HDLCompilers:246 - "count1.v" line 10 Reference to vector reg 'fx4out' is not a legal net lvalue
ERROR:HDLCompilers:102 - "count1.v" line 10 Connection to output port 'fout' must be a net lvalue
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谢谢了! |
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一只鸟敢站在脆弱的枝条上歇脚,它依仗的不是枝条不会断,而是自己有翅膀,会飞。
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