请教--我这个2.5分频的VHDL代码有什么问题么？为什么得不到仿真波形呀？

ncuhmily

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity fenpin is
port(inclk: in std_logic;
     present: in std_logic_vector(3 downto 0);
     outclk: buffer std_logic);
end entity fenpin;
architecture behav of fenpin is
signal clk,clk2:std_logic;
signal count:std_logic_vector(3 downto 0);
begin
clk<=inclk xor clk2;
process(clk)
begin
if(clk'event and clk='1')
   then if (count="0000")
   then count<=present-1;
        outclk<='1';
else
    count<=count-1;
    outclk<='0';
end if;
end if;
end process;
process(outclk)
begin
if(outclk'event and outclk='1')
then
clk2<=not clk2;
end if;
end process;
end behav;

仿真结果 (原文件名:1.jpg)

ncuhmily

已经解决了！自己太粗心了，没注意，呵呵！

仿真结果 (原文件名:1.jpg)

jeremygg

到底怎么是怎么回事啊，没看明白啊，楼主再解释一下吧，

sdram

clk2没有初始值.