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发表于 2010-6-4 07:57:50
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回复【1楼】wowbanui
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谢谢,我这儿板子上的数码管使能端固定了,不能动态扫描显示。要求就是在8个数码管上按从右到左的顺序循环显示hello。我的笨代码如下:
//top-level file
module hello(HEX7,HEX6,HEX5,HEX4,
HEX3,HEX2,HEX1,HEX0,
CLOCK_50,KEY);
input CLOCK_50;
input [0:0]KEY;
output [6:0]HEX7,HEX6,HEX5,HEX4,HEX3,HEX2,
HEX1,HEX0;
wire clk_1hz;
reg [3:0]cnt;
div u0(.o_clk(clk_1hz),
.rst_n(KEY),
.i_clk(CLOCK_50)
);
always @(posedge clk_1hz or negedge KEY)
begin
if(!KEY)
cnt<=4'b0;
else
begin
if(cnt==4'b0111)
cnt<=4'b0;
else
cnt<=cnt+1'b1;
end
end
seg7_h0 h0(.oseg(HEX0),
.idig(cnt)
);
seg7_h1 h1(.oseg(HEX1),
.idig(cnt)
);
seg7_h2 h2(.oseg(HEX2),
.idig(cnt)
);
seg7_h3 h3(.oseg(HEX3),
.idig(cnt)
);
seg7_h4 h4(.oseg(HEX4),
.idig(cnt)
);
seg7_h5 h5(.oseg(HEX5),
.idig(cnt)
);
seg7_h6 h6(.oseg(HEX6),
.idig(cnt)
);
seg7_h7 h7(.oseg(HEX7),
.idig(cnt)
);
endmodule
//divider
module div(
output reg o_clk,
input rst_n,
input i_clk
);
parameter N=50_000_000;
parameter M=24_999_999;
reg [25:0]cnt;
always @(posedge i_clk or negedge rst_n)
begin
if(!rst_n)
cnt<=26'b0;
else
begin
if(cnt==N-1)
cnt<=26'b0;
else
cnt<=cnt+26'b1;
end
end
always @(posedge i_clk or negedge rst_n)
begin
if(!rst_n)
o_clk<=0;
else
begin
if(cnt<=M)
o_clk<=1;
else
o_clk<=0;
end
end
endmodule
//seg7_lut
module seg7_h0
(
output reg [6:0] oseg,
input [3:0] idig
);
always @ (idig)
begin
case (idig)
4'h0: oseg = 7'b1000000; //O
//4'h1: oseg = 7'b1111001;
//4'h2: oseg = 7'b0100100;
//4'h3: oseg = 7'b0110000;
4'h4: oseg = 7'b0001001; //H
4'h5: oseg = 7'b0000110; //E
4'h6: oseg = 7'b1000111; //L
4'h7: oseg = 7'b1000111; //L
default: oseg = 7'b1111111;
endcase
end
endmodule
。。。。。。
//seg7_lut
module seg7_h7
(
output reg [6:0] oseg,
input [3:0] idig
);
always @ (idig)
begin
case (idig)
4'h7: oseg = 7'b1000000; //O
//4'h1: oseg = 7'b1111001;
//4'h2: oseg = 7'b0100100;
//4'h3: oseg = 7'b0110000;
4'h3: oseg = 7'b0001001; //H
4'h4: oseg = 7'b0000110; //E
4'h5: oseg = 7'b1000111; //L
4'h6: oseg = 7'b1000111; //L
default: oseg = 7'b1111111;
endcase
end
endmodule |
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