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//大学时候写的，虽然很简单但是还是拿出来晒一下
/*/////////////////////////////////////////////////////////////
德州da芯片tlv5618（12位串行输入，双通道输出） 的verilog代码，
/////////////////////////////////////////////////////////////*/
module tlv5618(
sys_clk, //系统时钟50M
da_rest, //复位端
da_start, //转换控制端
da_bus, //da数据总线
/*输出端*/
da_out, //接da串行数据输入端
da_clk, //接da时钟输入端
da_cs //接da片选输入端
);
/////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////
input sys_clk,da_rest,da_start;
input [11:0]da_bus;
output da_out,da_clk,da_cs;
parameter idle=3'b001;
parameter load_d=3'b010;
parameter send=3'b100;
reg da_cs;
reg shift;
reg clear;
reg load;
reg [2:0] state;
reg [2:0] next_state;
reg [5:0] bit_counter;
reg [15:0] data_shfreg;
reg da_clk_en;
/////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////
assign da_out=data_shfreg[15];
assign da_clk=da_clk_en?sys_clk:0;
reg[2:0] da_start_reg;
always @ ( posedge sys_clk or negedge da_rest )
if(!da_rest)
da_start_reg <= 3'b000;
else
da_start_reg <= {da_start_reg[1:0],da_start};
wire da_start_en;
assign da_start_en = ( da_start_reg[2:1] == 2'b01 ) ;
always@(state or bit_counter or da_start_en)
begin
load=0;
shift=0;
next_state=state;
case(state)
idle:
if(da_start_en==1)
begin
da_clk_en=0;
da_cs=1;
next_state=load_d;
end
else
begin
da_clk_en=0;
da_cs=1;
next_state=idle;
end
load_d:
begin
load=1;
da_cs=0;
next_state=send;
end
send:
if(bit_counter<=15)
begin
da_clk_en=1;
shift=1;
end
else
begin
da_cs=1;
da_clk_en=0;
next_state=idle;
end
default next_state=idle;
endcase
end
always @(posedge sys_clk or negedge da_rest)
if(!da_rest)state<=idle;else state <=next_state;
always @(posedge sys_clk or negedge da_rest)
begin
if(!da_rest)
begin
data_shfreg<=0;
bit_counter<=0;
end
else
begin
if(load)
begin
data_shfreg<={4'b0100,da_bus[11:0]};
bit_counter<=0;
end
if(shift)
begin
bit_counter<=bit_counter+1;
data_shfreg<={data_shfreg[14:0],1'b0};
end
end
end
endmodule |
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发表于 2011-12-20 10:19:28
