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模块比较简单，直接粘代码了
module spi_module(
CLK,
SSEL, SCK, MOSI, MISO,
byte_received, byte_data_received, byte_data_sent
);
input CLK;
// SPI Interface
input SSEL;
input SCK;
input MOSI;
output MISO;
// FPGA Interface
input [7:0] byte_data_sent;
output byte_received;
output [7:0] byte_data_received;
reg [3:0] bitcnt;
reg [7:0] byte_data_received_w;
always @(posedge SCK or posedge SSEL)
begin
if(SSEL)begin
bitcnt <= 4'b0000;
end
else begin
bitcnt <= bitcnt + 4'b0001;
byte_data_received_w <= {byte_data_received_w[6:0], MOSI};
end
end
wire byte_received_w = (~SSEL) && (bitcnt == 4'b1000);
reg [7:0] byte_data_sentr;
always @(negedge SCK or posedge SSEL)
begin
if(SSEL)
byte_data_sentr <= byte_data_sent;
else begin
if(bitcnt == 3'b000)
byte_data_sentr <= 8'h00;
else
byte_data_sentr <= {byte_data_sentr[6:0],1'b0};
end
end
assign MISO = byte_data_sentr[7];
reg [2:0]byte_received_r; always @(posedge CLK) byte_received_r <= {byte_received_r[1:0],byte_received_w};
assign byte_received = (byte_received_r[2:1]==2'b01);
reg [7:0] byte_data_received_r[1:0];
always @(posedge CLK)
begin
byte_data_received_r[0] <= byte_data_received_w;
byte_data_received_r[1] <= byte_data_received_r[0];
end
assign byte_data_received = byte_data_received_r[1];
endmodule
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发表于 2015-7-21 17:32:03
楼主
