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发表于 2019-1-8 14:09:58
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本帖最后由 Earthman 于 2019-1-8 14:15 编辑
armcortex-m4 reference manual-about debug还提供了额外的CPUID register 查看cpu版本
To identify the Cortex-M4 processor within the CoreSight system, ARM recommends that a debugger perform the following actions:
Locate and identify the Cortex-M4 ROM table using its CoreSight identification. See Table 8.1 for more information.
Follow the pointers in that Cortex-M4 ROM table:
System Control Space (SCS)
Breakpoint unit (BPU)
Data watchpoint unit (DWT).
See Table 8.2 for more information.
When a debugger identifies the SCS from its CoreSight identification, it can identify the processor and its revision number from the CPUID register in the SCS at address 0xE000ED00. |
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