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发表于 2008-1-1 12:50:52
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity anti_15ms_glitch is
port(
rst : in std_logic;
clk : in std_logic;
flag_1ms : in std_logic;
in_signal : in std_logic;
out_signal : out std_logic
);
end anti_15ms_glitch;
architecture behavioral of anti_15ms_glitch is
type state is (idle,wait_high,signal_out,wait_low);
signal prt_state : state;
signal counter : std_logic_vector(3 downto 0);
begin
process(rst,clk) -- generate out_signal signal
begin
if rst = '0' then
out_signal <= '0';
counter <= "0000";
prt_state <= idle;
elsif clk'event and clk = '1' then
case prt_state is
when idle =>
out_signal <= '0';
counter <= "0000";
if in_signal = '1' then
prt_state <= wait_high;
end if;
when wait_high =>
if counter = "1111" then --delay 15ms
if in_signal = '1' then
prt_state <= signal_out;
else
prt_state <= idle;
end if;
else
if flag_1ms = '1' then
counter <= counter + 1;
end if;
end if;
when signal_out =>
out_signal <= '1';
counter <= "0000";
if in_signal = '0' then
prt_state <= wait_low;
end if;
when wait_low =>
if counter = "1111" then --delay 15ms
if in_signal = '1' then
prt_state <= signal_out;
else
prt_state <= idle;
end if;
else
if flag_1ms = '1' then
counter <= counter + 1;
end if;
end if;
when others =>
prt_state <= idle;
end case;
end if;
end process;
end behavioral; |
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