|
楼主 |
发表于 2009-7-15 12:05:19
|
显示全部楼层
entity CLKDIV is
------------------------------------------
generic ( n: integer := 60 );
port (
CLK_IN : in std_logic;
CLK_RST: in std_logic;
CLK_CS : in std_logic;
CLK_OUT: out std_logic
);
------------------------------------------
end CLKDIV;
architecture Behavioral of CLKDIV is
------------------------------------------
signal CLK_CLK: std_logic;
------------------------------------------
begin
------------------------------------------
div: process ( CLK_RST,CLK_IN,CLK_CS )
variable CLK_CNT: integer range 0 to 511 := n;
begin
if ( CLK_RST = '0' ) then
CLK_CLK <= '0';
CLK_CNT := 0;
elsif ( CLK_IN' event and CLK_IN = '1' and CLK_CS = '0' ) then
CLK_CLK <= '0';
CLK_CNT := CLK_CNT + 1;
if ( CLK_CNT = n ) then
CLK_CLK <= '1';
CLK_CNT := 0;
end if;
end if;
end process div;
CLK_OUT <= CLK_CLK;
------------------------------------------
end Behavioral; |
|