|
我按照Pdf上的教程写了一次仿真测试的程序,但仿真时出错了,程序如下:
module stimulus;
wire q,qbar;
reg set,reset;
SR_latch mq(q,qbar,set,reset);
initial
begin
$monitor($time,"set=%b,reset=%b,q=%b\n",set,reset,q);
set=0;reset=0;
#5 reset=1;
#5 reset=0;
#5 set=1;
end
endmodule
module SR_latch(Q,Qbar,Sbar,Rbar);
output Q,Qbar;
input Sbar,Rbar;
nand n1(Q,Sbar,Qbar);
nand n2(Qbar,Rbar,Q);
endmodule
仿真结果如下:
Error: Run Analysis and Synthesis (quartus_map) through Technology Mapping followed by Timing Analyzer (quartus_tan) on top level entity "stimulus" before running timing simulation in Simulator (quartus_sim)
我已经问了好多人了,他们都不会。请高手指点一下我,我不甚感激! |
阿莫论坛20周年了!感谢大家的支持与爱护!!
一只鸟敢站在脆弱的枝条上歇脚,它依仗的不是枝条不会断,而是自己有翅膀,会飞。
|